Synchronous rectifier and controller for inductive coupling

• US 7,920,396 B2
• Filed: 07/13/2007
• Issued: 04/05/2011
• Est. Priority Date: 07/13/2007
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Knight, Jonathan Robert
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US11/777,710
• Publication Number:
  US 20090016090A1
• Time in Patent Office: 1,362 Days
• Field of Search: 323/235, 323/282, 323/283, 323/351, 363/125, 363/127
• US Class Current: 363/127
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A synchronous rectifier is arranged to rectify inductively coupled power using FETs (field effect transistors) to minimize the voltage drop of the rectifier, which minimizes power loss. Power loss is an important consideration in applications where fairly significant power is coupled to a device (such as a battery charger or other energy storage device) for a fairly short time (such as less than one hour) at a fairly low voltage (such as around 2.5 to 4.5 volts). Body diodes of the FETs can be used to supply power for bootstrapping and control logic for controlling the FETs.

Claims

1. A synchronous switch circuit, comprising:

an inductor configured to generate an alternating current voltage in response to a received changing electromagnetic field;

a synchronous rectifier comprising first and second high side switches and first and second low side switches that are configured to rectify the alternating current voltage to produce a direct current voltage;

an energy storage device configured to store energy from the direct current voltage; and

control circuitry configured to control the first and second high side switches and the first and second low side switches in response to a state of the alternating current voltage.

2. The circuit of claim 1, wherein:

the first low side switch and the first high side switch are configured to be activated when the state of the alternating current voltage is a positive-going zero crossing; and

the second low side switch and the second high side switch are configured to be activated when the state of the alternating current voltage is a negative-going zero crossing.

3. The circuit of claim 2, wherein:

the first high side switch is configured to be activated when a voltage level of the alternating current voltage with a first polarity is greater than a voltage of a power terminal of the energy storage device; and

the second high side switch is configured to be activated when a voltage level of the alternating current voltage with a second polarity is greater than the voltage of the power terminal of the energy storage device.

4. The circuit of claim 3, wherein the control circuitry comprises a latch configured to latch a result of a comparison of the voltage level having the first polarity and the voltage of the power terminal of the energy storage device.

5. The circuit of claim 1, further comprising:

a regulator that is coupled to a power node of the energy storage device and configured to provide power for the control circuitry.

6. The circuit of claim 5, wherein the regulator comprises a low dropout voltage regulator.

7. The circuit of claim 5, wherein the regulator comprises a buck-boost switching regulator.

8. The circuit of claim 5, wherein:

each of the first and second low side switches comprises an NMOS transistor;

each of the first and second high side switches comprises a PMOS transistor;

the NMOS transistors comprise body diodes configured to perform low side rectification;

the PMOS transistors comprise body diodes configured to perform high side rectification; and

the NMOS and PMOS transistors are configured to perform the rectification to provide power to the power node of the energy storage device.

9. The circuit of claim 5, wherein:

each of the first and second low side switches and each of the first and second high side switches comprises an NMOS transistor;

the first and second high side switches are isolated from a substrate that is common with the first and second low side switches;

the NMOS transistors comprise body diodes configured to perform rectification; and

the NMOS transistors are configured to perform the rectification to provide power to the power node of the energy storage device.

10. The circuit of claim 5, wherein:

each of the first and second low side switches and each of the first and second high side switches comprises an NMOS transistor;

backgates of the first and second high side switches and backgates of the first and second low side switches are coupled to a common substrate;

each of the first and second high side switches comprises a body diode coupled across a source and a drain of that high side switch; and

the body diodes are configured to perform rectification of the alternating current voltage so as to provide power to the power node of the energy storage device.

11. A method for synchronous rectification, comprising:

inductively coupling a power signal to first and second input terminals;

generating a direct current voltage by (i) activating a first low side switch and a first high side switch when a state of the power signal is a positive-going zero crossing and (ii) activating a second low side switch and a second high side switch when the state of the power signal is a negative-going zero crossing;

storing energy from the direct current voltage in an energy storage device; and

providing power from the energy storage device to control logic that activates the first and second high side switches and the first and second low side switches.

12. The method of claim 11, wherein the energy storage device comprises a capacitor.

13. The method of claim 11, wherein:

activating the first high side switch comprises activating the first high side switch when a voltage level at the first input terminal is greater than a voltage of a power terminal of the energy storage device; and

activating the second high side switch comprises activating the second high side switch when a voltage level at the second input terminal is greater than the voltage of the power terminal of the energy storage device.

14. The method of claim 11, further comprising:

regulating a voltage from the energy storage device to provide the power to the control logic.

15. The method of claim 11, wherein:

each of the first and second low side switches comprises an NMOS transistor;

each of the first and second high side switches comprises a PMOS transistor;

the NMOS transistors comprise body diodes that perform low side rectification;

the PMOS transistors comprise body diodes that perform high side rectification; and

the NMOS and PMOS transistors perform the rectification of the NMOS and PMOS to provide power to a power node of the energy storage device.

16. The method of claim 11, wherein:

each of the first and second low side switches and each of the first and second high side switches comprises an NMOS transistor;

the first and second high side switches are isolated from a substrate that is common with the first and second low side switches;

the NMOS transistors comprise body diodes that perform rectification; and

the NMOS transistors perform the rectification to provide power to a power node of the energy storage device.

17. The method of claim 11, wherein:

each of the first and second low side switches and each of the first and second high side switches comprises an NMOS transistor;

backgates of the first and second high side switches and backgates of the first and second low side switches are coupled to a common substrate;

each of the first and second high side switches comprises a body diode coupled across a source and a drain of that high side switch; and

the body diodes perform rectification of the alternating current voltage so as to provide power to a power node of the energy storage device.

18. A synchronous switch, comprising:

a means for inductively coupling a power signal to first and second input terminals;

a means for generating a direct current voltage by (i) activating a first low side switch and a first high side switch when a state of the power signal is a positive-going zero crossing and (ii) activating a second low side switch and a second high side switch when the state of the power signal is a negative-going zero crossing;

a means for storing energy from the direct current voltage; and

a means for providing power from the means for storing energy to control logic for activating the first and second high side switches and the first and second low side switches.

19. The synchronous switch of claim 18, wherein the means for storing energy comprises a capacitor.

20. The synchronous switch of claim 18, wherein:

body diodes of the first and second low side switches and body diodes of the first and second high side switches are configured to rectify the inductively coupled power signal to generate power for bootstrapping the control logic.