Converting SRAM cells to ROM cells

• US 7,920,411 B2
• Filed: 02/25/2009
• Issued: 04/05/2011
• Est. Priority Date: 02/25/2009
• Status: Expired due to Fees

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Chang, Ingming, Wang, Karl Lin
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US12/379,616
• Publication Number:
  US 20100214824A1
• Time in Patent Office: 769 Days
• Field of Search: 365/94, 365/104
• US Class Current: 365/156
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/146 Write once memory, i.e. allowing changing of memory content by writing additional bits

Abstract

A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged as two cross coupled inverters. It is converted to a read only memory cell by severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value.

Claims

1. A method of converting a static random access memory cell comprising a data retention portion powered by a higher and lower voltage supply line and comprising four transistors arranged as two cross coupled inverters to a read only memory cell said method comprising:

severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value, and

severing a connection between a further transistor within a second of said two inverters and another of said voltage supply lines such that when powered said second inverter outputs a different predetermined value to said first inverter.

2. A method according to claim 1, wherein said step of severing said connection comprises removing a via connecting said voltage supply line to said transistor.

3. A method according to claim 1, wherein said step of severing said connection comprises severing a metallisation layer connecting said voltage supply line to said transistor.

4. A method of converting a static random access memory cell comprising a data retention portion powered by a higher and lower voltage supply line and comprising four transistors arranged as two cross coupled inverters to a read only memory cell said method comprising:

severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value, wherein said static random access memory cell further comprises two access transistors having different threshold voltages linking said data retention portion to respective bit lines, said static random access memory being a single ended sensing memory cell, and

severing a connection between an output of said access transistor having a higher threshold voltage and one of said bit lines, said one of said bit lines being a bit line held at a predetermined voltage.

5. A data storage cell comprising supply voltage lines connectable to a higher voltage source and a lower voltage source for powering said data storage cell, said data storage cell comprising:

a data retention portion;

said data retention portion comprising four transistors arranged as two cross coupled inverters, such that when powered a higher or lower voltage value is output from a first of said two inverters and the other lower or higher voltage value is output by a second of said two inverters, wherein said first inverter is arranged to be powered by only one of said two voltage sources, such that when said data storage cell is powered said first inverter outputs a predetermined one of said higher or lower voltage value dependent upon said voltage source powering said first inverter.

6. A data storage cell according to claim 5, wherein said second inverter is arranged to be powered by only one of said two voltage sources, said first and second inverters being powered by different voltage sources such that when powered said first and second inverters respectively each output a different one of said higher and said lower voltage value.

7. A data storage cell according to claim 5, said data storage cell further comprising two output nodes for outputting data and two access transistors each responsive to a control signal to connect said two outputs of said two inverters to said two output nodes.

8. A data storage cell according to claim 7, wherein said access transistors comprise nmos transistors.

9. A data storage cell according to claim 5, wherein each of said two inverters comprises a pmos transistor stacked on an nmos transistor;

a first of said two inverters having a source of said pmos transistor connected to said higher voltage supply line and a drain of said nmos transistor floating, such that when powered said inverter outputs a higher voltage value from a node between said stacked transistors;

and a second of said two inverters having a source of said pmos transistor floating and a drain of said nmos transistor connected to said lower voltage supply line, such that when powered said inverter outputs a lower voltage value from a node between said stacked transistors.

10. A data storage cell according to claim 5, said data storage cell further comprising an output node for outputting data from said data storage cell and two access transistors, a first access transistor being responsive to a control signal to connect an output of a first of said two inverters to said output node, and a second access transistor having a higher threshold voltage than said first access transistor and being connected to an output of said second inverter.

11. A data storage cell according to claim 10, wherein each of said two inverters comprises a pmos transistor stacked on an nmos transistor;

a first of said two inverters having a source of said pmos transistor floating and a drain of said nmos transistor connected to said lower voltage source, such that said first inverter outputs said lower voltage value from a node between said stacked transistors via said first access transistor to an output node; and

said second access transistor being arranged to link said output of said second inverter to a line tied to said higher voltage supply line.

12. A data storage cell according to claim 10, said second access transistor having a floating output such that said output of said second inverter is not connected to an output line;

wherein each of said two inverters comprise a pmos transistor stacked on an nmos transistor;

a first of said two inverters having a source of said pmos transistor connected to said higher voltage source and a drain of said nmos transistor connected to said lower voltage level, such that said inverter outputs said higher voltage value from a node between said stacked transistors via said first access transistor to an output node;

and a second of said two inverters having a source of said pmos transistor floating and a drain of said nmos transistor connected to said lower voltage source, such that said inverter comprises said lower voltage value at a node between said stacked transistors.

13. A data storage cell according to claim 10, wherein said access transistors comprise nmos transistors.

14. A data storage cell according to claim 5, wherein said data storage cell is compatible with a static random access memory cell and occupies a same area as said static random access memory cell.

15. A memory comprising a plurality of data storage cells arranged in an array, at least some of said data storage cells comprising data storage cells according to claim 5, said memory further comprising:

at least one bit line associated with each column of said array; and

at least one word line associated with each row of said array;

wherein

an output of a first inverter of each of said memory cells in a column is in data communication with a respective bit line via a respective access transistor, said respective access transistors communicating said outputs of said first inverters to said bit line in response to a control value received at a gate of said access transistor, said control value being sent via said at least one word line to all access transistors in a row of said array.

16. A memory according to claim 15, said plurality of data storage cells comprising at least some SRAM cells.