Semiconductor memory device

• US 7,920,417 B2
• Filed: 06/30/2009
• Issued: 04/05/2011
• Est. Priority Date: 05/13/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Rho, Kwang-Myoung, Seo, Woo-Hyun
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US12/494,344
• Publication Number:
  US 20100290280A1
• Time in Patent Office: 644 Days
• Field of Search: 365/210.11, 365/211
• US Class Current: 365/171
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A semiconductor memory cell includes a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines, a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding variation of the read current according to the data and a current controller connected to a current path of the read current and configured to control a current amount of the read current.

Claims

1. A semiconductor memory cell comprising:

a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines;

a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding variation of the read current according to the data; and

a current controller connected to a current path of the read current and configured to control a current amount of the read current.

2. The semiconductor memory device of claim 1, further comprising a write driver configured to drive the first and second driving lines with power corresponding the data.

3. The semiconductor memory device of claim 1, wherein the current controller includes:

a control signal generator configured to generate a current control signal corresponding to the temperature information; and

a current adjuster configured to adjust a current amount of the read current in response to the current control signal.

4. The semiconductor memory device of claim 3, wherein the current control signal has a voltage level corresponding to the temperature information.

5. The semiconductor memory device of claim 3, wherein the control signal generator includes:

a selection signal generator configured to generate a selection signal corresponding to the temperature information;

a voltage generator configured to generate a plurality of bias voltages; and

a multiplexer configured to output one of the plurality of bias voltages as the current control signal corresponding to the selection signal.

6. The semiconductor memory device of claim 1, wherein each of the plurality of memory cells includes:

a switch configured to perform a switching operation in response to an address; and

a magnetic tunnel junction device connected to the switch.

7. A semiconductor memory device, comprising:

a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in a source line and a bit line;

a cell current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding to variation of the read current according to the data;

a current controller connected to a current path of the read current and configured to control a current amount of the read current according to temperature information;

a plurality of reference memory cell groups configured to store reference data having polarity corresponding to a direction of current flowing in a reference source line and a reference bit line;

a reference current generator configured to generate a predetermined current, apply the predetermined current to the plurality of reference memory cells, and generate a reference current corresponding to the reference data;

a reference current controller configured to control current applied to the plurality of reference memory cells according to the temperature information in the reference current generator; and

a sense amplifier configured to sense and amplify the data current and the reference current.

8. The semiconductor memory device of claim 7, further comprising:

a first write driver configured to drive the source line and the bit line with power corresponding the data; and

a second write driver configured to drive the reference source line and the reference bit line based on power corresponding to the reference data.

9. The semiconductor memory device of claim 7, wherein each of the current controller and the reference current controller includes a current adjuster configured to adjust a current amount of a corresponding current according to the temperature information.

10. The semiconductor memory device of claim 9, further comprising a control signal generator configured to generate a current control signal corresponding to the temperature information and control the current adjuster.

11. The semiconductor memory device of claim 10, wherein the current control signal has a voltage level corresponding to the temperature information.

12. The semiconductor memory device of claim 10, wherein the control signal generator includes:

a selection signal generator configured to generate a selection signal corresponding to the temperature information;

a voltage generator configured to generate a plurality of bias voltages; and

a multiplexer configured to output one of the plurality of bias voltages corresponding to the selection signal.

13. The semiconductor memory device of claim 7, wherein each of the plurality of memory cells includes:

a switch configured to perform a switching operation in response to an address; and

a magnetic tunnel junction device connected to the switch.

14. The semiconductor memory device of claim 7, wherein each of the plurality of reference memory cell groups includes:

first and second switches configured to perform a switching operation in response to an address; and

first and second magnetic tunnel junction devices connected to the first and second switches respectively.

15. The semiconductor memory device of claim 14, wherein the first and second magnetic tunnel junction devices store data having different polarities.