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Digital adaptation circuitry and methods for programmable logic devices

  • US 7,920,621 B2
  • Filed: 09/14/2006
  • Issued: 04/05/2011
  • Est. Priority Date: 09/14/2006
  • Status: Active Grant
First Claim
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1. A method of controlling equalization of an incoming data signal, the method comprising:

  • determining symbol intervals of the incoming data signal, the determining occurring at a first update rate;

    selecting a pattern of bits based, at least in part, on a convergence time of the incoming data signal;

    detecting a plurality of sets of two successive differently valued bits in the data signal, wherein each detected set of two successive differently valued bits is contained within a sequence of bits matching the selected pattern;

    providing values indicating whether transitions in the incoming data signal between the two bits of each of the plurality of sets are late or early;

    integrating the provided values over time; and

    updating, at a second update rate, the equalization of the incoming data signal based on (1) the integration of the values and (2) the determined symbol intervals.

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