Digital adaptation circuitry and methods for programmable logic devices

• US 7,920,621 B2
• Filed: 09/14/2006
• Issued: 04/05/2011
• Est. Priority Date: 09/14/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Shumarayev, Sergey, Chan, Doris Po Ching, Lai, Tin H., Tran, Thungoc M., Wong, Wilson, Hoang, Tim Tri, Maangat, Simardeep
• Primary Examiner(s): Fan; Chieh M
• Assistant Examiner(s): Joseph; Jaison
• Application Number:
  US11/522,284
• Publication Number:
  US 20080069276A1
• Time in Patent Office: 1,664 Days
• Field of Search: 375/229, 375/230, 375/231, 375/232
• US Class Current: 375/229
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

Claims

1. A method of controlling equalization of an incoming data signal, the method comprising:

determining symbol intervals of the incoming data signal, the determining occurring at a first update rate;

selecting a pattern of bits based, at least in part, on a convergence time of the incoming data signal;

detecting a plurality of sets of two successive differently valued bits in the data signal, wherein each detected set of two successive differently valued bits is contained within a sequence of bits matching the selected pattern;

providing values indicating whether transitions in the incoming data signal between the two bits of each of the plurality of sets are late or early;

integrating the provided values over time; and

updating, at a second update rate, the equalization of the incoming data signal based on (1) the integration of the values and (2) the determined symbol intervals.

2. The method defined in claim 1 further comprising:

decreasing the equalization of the incoming data signal if a transition between two bits of one of the plurality of sets is early.

3. The method defined in claim 1 wherein said providing and said integrating are performed only when a predetermined pattern of successive bit values precedes the transition.

4. The method defined in claim 3 wherein the predetermined pattern includes a plurality of similarly valued bits.

5. The method defined in claim 1 wherein the detecting and providing are performed repeatedly, and wherein the updating is performed only when, in a plurality of performances of the detecting and providing, the transitions are more often late than early.

6. The method defined in claim 5 wherein, if, in the plurality of performances of the detecting and providing, the transitions are more often early than late, then decreasing the equalization of the incoming data signal.

7. The method defined in claim 1 wherein the providing comprises:

sampling the data signal when the transition should be occurring to produce a transition sample; and

comparing the transition sample to a reference value.

8. The method defined in claim 7 further comprising:

deriving the reference value from one of the two successive differently valued bits of one of the plurality of sets.

21. The method defined in claim 1 wherein the second update rate is user programmable.

9. A method of controlling equalization of an incoming data signal, the method comprising:

determining symbol intervals of the incoming data signal, the determining occurring at a first update rate;

selecting a pattern of bits based, at least in part, on a convergence time of the incoming data signal;

sampling the incoming data signal at times when data values in that signal should be stable, to produce data samples;

sampling the incoming data signal at times when that signal should be in transition between successive data values that are different from one another, to produce transition samples, wherein the successive data values correspond to bits contained within a sequence of bits matching the selected pattern;

comparing a transition sample taken between two successive differently valued data samples to a reference value;

integrating the result of the comparing over a plurality of successive performances of the comparing; and

updating, at a second update rate, the equalization based on (1) a result of the integrating and (2) the determined symbol intervals.

10. The method defined in claim 9 wherein the reference value is one of the two successive differently valued data samples.

11. The method defined in claim 10 wherein the controlling comprises:

increasing the equalization if the comparing shows that the transition sample has a value that is the same as the value of the first of the two successive data samples.

12. The method defined in claim 10 wherein the controlling comprises:

decreasing the equalization if the comparing shows that the transition sample has a value that is the same as the value of the second of the two successive data samples.

13. The method defined in claim 9 further comprising:

examining the incoming data signal for a pattern of successive data samples that includes a plurality of similarly valued data samples followed by a differently valued data sample; and

performing the comparing only in response to detection of the pattern.

14. The method defined in claim 13 wherein the comparing is performed using the transition sample between the differently valued data sample and the plurality of similarly valued data samples.

15. Circuitry for equalizing an incoming data signal, the circuitry comprising:

synchronization circuitry for determining symbol intervals of the incoming data signal, the determining occurring at a first update rate;

selection circuitry for selecting a pattern of bits based, at least in part, on a convergence time of the incoming data signal;

first sampling circuitry for sampling the incoming data signal at times when data values in that signal should be stable, to produce data samples;

second sampling circuitry for sampling the incoming data signal at times when that signal should be in transition between successive data values that are different from one another, to produce transition samples, wherein the successive data values correspond to bits contained within a sequence of bits matching the selected pattern;

comparison circuitry for comparing a transition sample taken between two successive differently valued data samples to a reference value;

circuitry for integrating an output of the comparison circuitry over time and for using a result of the integrating to determine whether to change equalization of the incoming data signal; and

equalization control circuitry for updating, at a second update rate, the equalization of the incoming data signal based on (1) the determination of whether to change the equalization and (2) the determined symbol intervals.

16. The circuitry defined in claim 15 wherein the reference value is one of the two successive differently valued data samples.

17. The circuitry defined in claim 16 wherein the equalization control circuitry increases the equalization if the transition sample has a value that is the same as the value of the first of the two successive data samples.

18. The circuitry defined in claim 16 wherein the equalization control circuitry decreases the equalization if the transition sample has a value that is the same as the value of the second of the two successive data samples.

19. The circuitry defined in claim 15 further comprising:

pattern detection circuitry for detecting occurrence of a predetermined pattern of values in a plurality of successive ones of the data samples and for enabling the equalization control circuitry when that pattern is detected.

20. The circuitry defined in claim 19 wherein the predetermined pattern comprises multiple similarly valued data samples followed by a differently valued data sample.

22. The circuitry defined in claim 15 wherein the first sampling circuitry comprises a first plurality of registers and the second sampling circuitry comprises a second plurality of registers, further comprising:

a third plurality of registers, wherein;

an output of one of the first plurality of registers is coupled to at least two registers of the third plurality of registers;

outputs of the second plurality of registers are each coupled to a different one of the third plurality of registers; and

wherein the comparison circuitry comprises decision logic circuitry coupled to outputs of the third plurality of registers, wherein the decision logic circuitry outputs a signal indicating whether to change equalization.

23. The circuitry defined in claim 22 further comprising:

pattern detection circuitry coupled the outputs of the third plurality of registers for detecting occurrence of a predetermined pattern of values in the third plurality of registers and for enabling the equalization control circuitry when that pattern is detected.