High speed processing of financial information using FPGA devices

• US 7,921,046 B2
• Filed: 06/19/2007
• Issued: 04/05/2011
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Exegy Incorporated
• Original Assignee: Exegy Incorporated
• Inventors: Chamberlain, Roger D., Schuehler, David Vincent, Parsons, Scott, Taylor, David E., Franklin, Mark A.
• Primary Examiner(s): Borlinghaus; Jason M
• Application Number:
  US11/765,306
• Publication Number:
  US 20080243675A1
• Time in Patent Office: 1,386 Days
• Field of Search: None
• US Class Current: 705/35
• CPC Class Codes: G06Q 40/00 Finance; Insurance; Tax strategies; Processing of corporate or income taxes
• CPC Class Codes: G06Q 40/04 Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

Methods and systems for processing financial market data using reconfigurable logic are disclosed. Various functional operations to be performed on the financial market data can be implemented in firmware pipelines to accelerate the speed of processing. Also, a combination of software logic and firmware logic can be used to efficiently control and manage the high speed flow of financial market data to and from the reconfigurable logic.

Claims

1. An apparatus for processing financial market data, the apparatus comprising:

a reconfigurable logic device with firmware logic deployed thereon, the firmware logic being configured to perform a specified data processing operation on the financial market data; and

a processor in communication with the reconfigurable logic device, the processor being programmed with software logic, the software logic being configured to (1) receive the financial market data as an input, and (2) manage a flow of the received financial market data into and out of the reconfigurable logic device.

2. The apparatus of claim 1 wherein the financial market data comprises a plurality of financial market data messages, and wherein the software logic is further configured to manage the flow of the received financial market data into and out of the reconfigurable logic device such that each message passes only once from the software logic to the firmware logic.

3. The apparatus of claim 1 wherein the financial market data comprises a plurality of financial market data messages, and wherein the software logic is further configured to manage the flow of the received financial market data into and out of the reconfigurable logic device such that each message passes only once from the firmware logic back to the software logic.

4. The apparatus of claim 1 wherein the financial market data comprises a plurality of financial market data messages, wherein processor is further configured to receive the financial market data messages from a plurality of different financial market data feeds, and wherein the software logic is further configured to (1) maintain a plurality of different thread groups simultaneously, (2) assign each financial market data message to a thread group based on a configuration file, wherein the configuration file is configured to associate each thread group with a different financial market data feed such that messages from a given one of the feeds will be processed by the thread group associated with that message'"'"'s feed, and (3) normalize the financial market data messages with the thread groups such that each thread group normalizes the financial market data messages assigned thereto independently of the other thread groups.

5. The apparatus of claim 1 wherein the financial market data comprises a plurality of financial market data messages, and wherein the software logic is further configured to (1) receive the financial market data messages destined for the firmware logic via a kernel mode process supported an operating system of the processor, and (2) transfer the financial market data messages destined for the firmware logic from the kernel mode process supported by an operating system of the processor to a user mode process supported by the operating system without a transition from a kernel space mode to a user address space mode by writing each received financial market data message destined for the firmware logic to a buffer that is mapped into both a kernel space and a user address space supported by the operating system.

6. The apparatus of claim 1 wherein the financial market data comprises a plurality of financial market data messages, and wherein the software logic further comprises a hardware interface driver and a data routing driver in communication with the hardware interface driver, wherein the hardware interface driver is configured to receive financial market data messages that have been processed by the firmware logic, and wherein the data routing driver is configured to (1) receive the firmware-processed financial market data messages from the hardware interface driver, (2) provide a first path and a second path for the firmware-processed financial market data messages, the first path comprising a path for the firmware-processed financial market data messages to at least one client through a network protocol stack, the second path comprising a path for the firmware-processed financial market data messages to an exceptions handling software module.

7. The apparatus of claim 6 wherein the data routing driver is further configured to interrogate at least a portion of the firmware-processed financial market data messages to determine the path over which each firmware-processed financial market data message should travel.

8. The apparatus of claim 1 wherein the software logic is further configured to issue a control command to the firmware logic in response to an instruction received by the processor from a client computer in communication therewith, the control command at least partially specifying the data processing operation to be performed by the firmware logic.

12. The apparatus of claim 2 wherein the firmware logic is further configured with a firmware pipeline that is configured to perform a plurality of different financial data processing operations on the received flow to thereby generate the flow of firmware-processed financial market data.

13. The apparatus of claim 12 further comprising a memory in which a plurality of financial instrument records are stored in memory addresses associated with a financial instrument symbology that is internal to the apparatus, wherein the reconfigurable logic is communication with the memory, wherein the financial market data messages relate to financial instruments, wherein the financial market data messages reference their related financial instruments using a financial instrument symbology that is different than the internal financial instrument symbology, and wherein the firmware logic is further configured to (1) convert each received financial market data message to the internal financial instrument symbology, (2) retrieve financial instrument records pertaining to the received financial market data messages from the memory using the internal financial instrument symbology for the received financial market data messages, and (3) update the financial instrument records in response to the financial data processing operations performed on the received financial market data messages.

16. The apparatus of claim 4 wherein the configuration file is further configured to associate at least one thread group with a plurality of different financial market data feeds.

17. The apparatus of claim 6 wherein the first path is wholly within a kernel space supported by the operating system of the processor.

18. The apparatus of claim 1 wherein the financial market data comprises a plurality of financial market data messages, and wherein the software logic comprises:

a protocol stack resident in a kernel space supported by an operating system of the processor, the protocol stack configured to receive the financial market data messages; and

a driver configured to connect, in the kernel space, to the protocol stack to access the financial market data messages.

19. The apparatus of claim 18 wherein the driver is further configured to write a plurality of financial market data messages destined for the firmware logic to a buffer that is mapped into both the kernel space and a user address space supported by the operating system of the processor.

20. The apparatus of claim 19 wherein the buffer comprises a plurality of input buffers that are mapped into both the kernel space and the user address space, each buffer being associated with a thread group, wherein the driver is further configured to (1) assign each of the plurality of financial market data messages destined for the firmware logic to a thread group from among a plurality of thread groups based on a configuration file, and (2) write each of the plurality of financial market data messages destined for the firmware logic to the buffer associated with its assigned thread group, and wherein each of the thread groups is configured to process, in the user address space, the financial market data messages present in its associated buffer independently of the other thread groups.

21. The apparatus of claim 20 wherein each of the thread groups is further configured to write its processed financial market data messages to an output buffer that is mapped into both the kernel space and the user address space, wherein the software logic further comprises a hardware interface driver resident in the kernel space, the hardware interface driver configured to transfer the processed financial market data messages from the output buffers to the firmware logic deployed on the reconfigurable logic device.

22. The apparatus of claim 21 wherein the protocol stack comprises a first protocol stack, and wherein the software logic further comprises:

a second protocol stack resident in the kernel space; and

a data routing driver configured to, in the kernel space, (1) receive financial market data messages from the reconfigurable logic device, (2) connect to the second protocol stack, and (3) selectively route a subset of the received financial market data messages to the second protocol stack for subsequent delivery to downstream clients.

9. A method for processing financial market data, the method comprising:

controlling with software logic a flow of financial market data from the software logic to and from firmware logic; and

performing a specified financial data processing operation on financial market data with firmware logic on a reconfiqurable logic device in response to the software logic controlling step.

10. The method of claim 9 wherein the financial market data comprises a plurality of financial market data messages, and wherein the controlling step further comprises controlling the flow of the financial market data such that each message passes only once from the software logic to the firmware logic.

11. The method of claim 9 wherein the financial market data comprises a plurality of financial market data messages, and wherein the controlling step further comprises controlling the flow of the financial market data such that each message passes only once from the firmware logic to the software logic.

14. The method of claim 10 wherein the performing step comprises performing with the firmware logic a plurality of different financial data processing operations on the received flow to thereby generate the flow of firmware-processed financial market data.

15. The method of claim 14 wherein the financial market data messages relate to financial instruments, wherein the financial market data messages reference their related financial instruments using a first financial instrument symbology, the method further comprising:

storing a plurality of financial instrument records in memory addresses associated with a second financial instrument symbology that is different than the first financial instrument symbology; and

using the firmware logic, (1) converting each received financial market data message to the second financial instrument symbology, (2) retrieving stored financial instrument records pertaining to the received financial market data messages using the second financial instrument symbology for the received financial market data messages, and (3) updating the financial instrument records in response to at least one of the financial data processing operations performed on the received financial market data messages.

23. The method of claim 9 wherein the financial market data comprises a plurality of financial market data messages, wherein a processor executes the software logic, the processor receiving the financial market data messages from a plurality of different financial market data feeds, and wherein the controlling step further comprises the software logic is (1) maintaining a plurality of different thread groups simultaneously, (2) assigning each financial market data message to a thread group based on a configuration file, wherein the configuration file associates each thread group with a different financial market data feed such that messages from a given one of the feeds will be processed by the thread group associated with that message'"'"'s feed, and (3) normalizing the financial market data messages with the thread groups such that each thread group normalizes the financial market data messages assigned thereto independently of the other thread groups.

24. The method of claim 23 wherein the configuration file associates at least one thread group with a plurality of different financial market data feeds.

25. The method of claim 9 wherein the financial market data comprises a plurality of financial market data messages, and wherein controlling step comprises the software logic:

receiving the financial market data messages destined for the firmware logic via a kernel mode process supported an operating system of the processor; and

transferring the financial market data messages destined for the firmware logic from the kernel mode process supported by an operating system of the processor to a user mode process supported by the operating system without a transition from a kernel space mode to a user address space mode by writing each received financial market data message destined for the firmware logic to a buffer that is mapped into both a kernel space and a user address space supported by the operating system.

26. The method of claim 9 wherein the financial market data comprises a plurality of financial market data messages, and wherein the software logic further comprises a hardware interface driver and a data routing driver in communication with the hardware interface driver, the hardware interface driver receiving financial market data messages that have been processed by the firmware logic, and the data routing driver (1) receiving the firmware-processed financial market data messages from the hardware interface driver, (2) providing a first path and a second path for the firmware-processed financial market data messages, the first path comprising a path for the firmware-processed financial market data messages to at least one client through a network protocol stack, the second path comprising a path for the firmware-processed financial market data messages to an exceptions handling software module.

27. The method of claim 26, the data routing driver interrogating at least a portion of the firmware-processed financial market data messages to determine the path over which each firmware-processed financial market data message should travel.

28. The method of claim 26 wherein the first path is wholly within a kernel space supported by the operating system of a processor.

29. The method of claim 9 wherein the controlling step further comprises the software logic issuing a control command to the firmware logic in response to an instruction received by the processor from a client computer in communication therewith, the control command at least partially specifying the data processing operation to be performed by the firmware logic.

30. The method of claim 9 wherein the financial market data comprises a plurality of financial market data messages, and wherein the software logic comprises a driver and a protocol stack resident in a kernel space supported by an operating system of a processor, the protocol stack receiving the financial market data messages, and the driver connecting, in the kernel space, to the protocol stack and accessing the financial market data messages.

31. The method of claim 30, the driver writing a plurality of financial market data messages destined for the firmware logic to a buffer that is mapped into both the kernel space and a user address space supported by the operating system of the processor.

32. The method of claim 31 wherein the buffer comprises a plurality of input buffers that are mapped into both the kernel space and the user address space, each buffer being associated with a thread group, the driver (1) assigning each of the plurality of financial market data messages destined for the firmware logic to a thread group from among a plurality of thread groups based on a configuration file, and (2) writing each of the plurality of financial market data messages destined for the firmware logic to the buffer associated with its assigned thread group, and each of the thread groups processing, in the user address space, the financial market data messages present in its associated buffer independently of the other thread groups.

33. The method of claim 32, each of the thread groups writing its processed financial market data messages to an output buffer that is mapped into both the kernel space and the user address space, wherein the software logic further comprises a hardware interface driver, the hardware interface driver transferring the processed financial market data messages from the output buffers to the firmware logic.

34. The method of claim 33 wherein the protocol stack comprises a first protocol stack, and wherein the software logic further comprises a second protocol stack resident in the kernel space and a data routing driver, the data routing driver performing the following steps in the kernel space:

(1) receiving financial market data messages from the reconfigurable logic device, (2) connecting to the second protocol stack, and (3) selectively routing a subset of the received financial market data messages to the second protocol stack for subsequent delivery to downstream clients.