Reconfigurable communications infrastructure for ASIC networks

• US 7,921,323 B2
• Filed: 11/16/2006
• Issued: 04/05/2011
• Est. Priority Date: 05/11/2004
• Status: Active Grant

• Current Assignee: Lionra Technologies Limited (Atlantic IP Services Limited)
• Original Assignee: L-3 Communications Integrated Systems LP (L3Harris Technologies, Inc.)
• Inventors: Yancey, Jerry W., Kuo, Yea Zong
• Primary Examiner(s): Baker; Stephen M
• Application Number:
  US11/600,934
• Publication Number:
  US 20070101242A1
• Time in Patent Office: 1,601 Days
• Field of Search: 714/4, 714/5
• US Class Current: 714/4.1
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

Reconfigurable communications infrastructures may be implemented to interconnect ASIC devices (e.g., FPGAs) and other computing and input/output devices using high bandwidth interconnection mediums. The computing and input/output devices may be positioned in locations that are physically segregated from each other, and/or may be provided to project a reconfigurable network across a wide area. The reconfigurable communications infrastructures may be implemented to allow such computing and input/output devices to be used in different arrangements and applications, e.g., for use in any application where a large array of ASIC devices may be usefully employed such as supercomputing, etc.

Claims

1. A method, comprising:

providing two or more separate signal processing circuits, each one of said two or more signal processing circuits including multiple ASIC devices that each includes a respective packet router;

providing a high bandwidth interconnection medium coupled between said signal processing circuits to form a reconfigurable communications infrastructure of said two or more signal processing circuits, the two or more signal processing circuits being selectively segregatable from each other, and the respective ASIC devices of each one of said two or more signal processing circuits being directly coupled to said high bandwidth interconnection medium by a respective common interface provided for the ASIC devices of each of said two or more signal processing circuits with no other processing device intervening between the high bandwidth interconnection medium and said respective ASIC devices; and

selectively communicating data between said two or more signal processing circuits by selectively routing data through the packet router of each of the respective ASIC devices of each one of said signal processing circuits across a first common interface to the high bandwidth interconnection medium and to an other one of said signal processing circuits through a second common interface to the packet router of each of the respective ASIC devices of said other one of said signal processing circuits without routing said data through any other intervening processing device between each respective ASIC device and the high bandwidth interconnection medium.

2. The method of claim 1, wherein each of said ASIC devices of said two or more signal processing circuits is an FPGA device.

3. The method of claim 2, further comprising providing said two or more signal processing circuits in positions physically segregated from each other;

and communicating data between said packet router of a respective one said FPGA devices of each of said two or more physically-segregated signal processing circuits across said first and second common interfaces and through said high bandwidth interconnection medium to the packet router of a respective FPGA device of an other one of said signal processing circuits without routing said data through any other intervening processing device between each respective FPGA device and the high bandwidth interconnection medium.

4. The method of claim 2, wherein each given one of said FPGA devices of one of said signal processing circuits comprises user-defined circuitry coupled to said respective packet router of said given one of said FPGA devices;

and wherein said method further comprises transmitting and receiving data packets between said user-defined circuitry of said given one of said FPGA devices of one of said signal processing circuits and an other one of said FPGA devices of an other different one of said signal processing circuits across said first and second common interfaces and through said high bandwidth interconnection medium.

5. The method of claim 2, wherein each given one of said FPGA devices of one of said signal processing circuits comprises at least one embedded processor coupled to said respective packet router of said given one of said FPGA devices;

and wherein said method further comprises transmitting and receiving data packets between said at least one embedded processor of said given one of said FPGA devices of one of said signal processing circuits and an other one of said FPGA devices of an other different one of said signal processing circuits across said first and second common interfaces and through said high bandwidth interconnection medium.

6. The method of claim 2, further comprising providing a vehicle-based reconfigurable communications infrastructure comprising a vehicle with each of said two or more signal processing circuits and said high bandwidth interconnection medium being positioned on or within said vehicle;

and communicating data between said two or more signal processing circuits through said packet routers of each of said FPGA devices of said two or more signal processing circuits across said first and second common interfaces and through said high bandwidth interconnection medium on or within said vehicle.

7. The method of claim 3, wherein said two or more signal processing circuits are physically segregated from each other by at least one of being positioned in different rooms of a given building or facility from each other, or being positioned in different compartments of a given mobile vehicle from each other.

8. The method of claim 2, wherein said high bandwidth interconnection medium comprises an optical transmission medium;

and wherein said method further comprises selectively communicating data between said two or more signal processing circuits by selectively routing data through the packet router of a respective FPGA device of each one of said two or more signal processing circuits across said first and second common interfaces and through said optical transmission medium to a respective FPGA device of an other different one of said signal processing circuits without routing said data through any other intervening processing device between each respective FPGA device and the high bandwidth interconnection medium.

9. The method of claim 2, further comprising selectively communicating data between said two or more signal processing circuits by selectively routing data through the packet router of a respective FPGA device of each one of said two or more signal processing circuits at a data transmission rate of greater than or equal to about 1 Gbps to a respective FPGA device of an other different one of said signal processing circuits without routing said data through any other intervening processing device between each respective FPGA device and the high bandwidth interconnection medium.

10. The method of claim 2, further comprising configuring each of said at least two separate signal processing circuits to perform different computing tasks in parallel.

11. The method of claim 2, wherein each of said signal processing circuits is a reconfigurable signal processing circuit that comprises two or more FPGA devices that each includes a packet router, said packet router of each one of said two or more FPGA devices of each given one of said signal processing circuits being coupled to each respective packet router of each of the other of said two or more FPGA devices of said same given one of said signal processing circuits;

and wherein said method further comprises using said packet router of each given one of said two or more FPGA devices of each given one of said signal processing circuits;

to communicate data packets within said given signal processing circuit by routing data packets to and from each other of said two or more FPGA devices of the same given one of said signal processing circuits without routing said data packets outside said given signal processing circuit across said first or second common interfaces to said high bandwidth interconnection medium.

12. The method of claim 11 wherein said packet router of each one of said two or more FPGA devices of each given one of said signal processing circuits is coupled to each respective packet router of each of the other of said two or more FPGA devices of same said same given one of said signal processing circuits by a separate respective duplex data communication link so as to form a direct serial interconnection between each two of said two or more FPGA devices of said same given one of said signal processing circuits;

and wherein said method further comprises using said packet router of each given one of said two or more FPGA devices of said each given one of said signal processing circuits to transmit and receive data packets across each of said separate respective duplex data communication links existing between said given one of said two or more FPGA devices and each other of said two or more FPGA devices of the same given one of said signal processing circuits without routing said data packets outside said given signal processing circuit across said first or second common interfaces to said high bandwidth interconnection medium.

13. The method of claim 2, further comprising:

providing said two or more separate signal processing circuits as a first signal processing circuit and a second signal processing circuit;

configuring said first and second signal processing circuits to perform a first computing task together as a first computing cluster;

providing at least two additional separate signal processing circuits as a third signal processing circuit including multiple FPGA devices and a fourth signal processing circuit including multiple FPGA devices, the first, second, third and fourth signal processing circuits being selectively segregatable from each other and each one of said respective FPGA devices of said third and fourth signal processing circuits being directly coupled to said high bandwidth interconnection medium by a respective common interface provided for the FPGA devices of each of said third and fourth signal processing circuits with no other processing device intervening between the high bandwidth interconnection medium and the FPGA devices of said respective third and fourth signal processing circuits;

dynamically configuring said third and fourth separate signal processing circuits in real time to perform a second computing task together as a second computing cluster, said second computing task being different than said first computing task; and

simultaneously performing said first computing task with said first computing cluster and said second computing task with said second computing cluster.

14. The method of claim 13, further comprising:

dynamically reconfiguring said first and third separate signal processing circuits in real time to perform a third computing task together as a third computing cluster;

dynamically configuring said second and fourth separate signal processing circuits in real time to perform a fourth computing task together as a fourth computing cluster, said fourth computing task being different than said third computing task; and

simultaneously performing said third computing task with said third computing cluster and said fourth computing task with said fourth computing cluster.

15. The method of claim 13, further comprising:

dynamically reconfiguring said first, second, third and fourth separate signal processing circuits in real time to perform a third computing task together as a third computing cluster; and

performing said third computing task with said third computing cluster.

16. A reconfigurable communications infrastructure, comprising:

two or more separate signal processing circuits, each one of said two or more signal processing circuits including at multiple ASIC devices that each includes a respective packet router; and

a high bandwidth interconnection medium coupled between said signal processing circuits to form said reconfigurable communications infrastructure of said two or more signal processing circuits, the two or more signal processing circuits being selectively segregatable from each other, and the respective ASIC devices of each one of said two or more signal processing circuits being directly coupled to said high bandwidth interconnection medium by a common interface provided for the ASIC devices of each of said two or more signal processing circuits with no other processing device intervening between the high bandwidth interconnection medium and said respective ASIC devices; and

wherein the reconfigurable communications infrastructure is configured to selectively communicate data between said two or more signal processing circuits by selectively routing data through the packet router of each of the respective ASIC devices of each one of said signal processing circuits across a first common interface said high bandwidth interconnection medium to an other one of said signal processing circuits through a second common interface to the packet router of each of the respective ASIC devices of said other one of said signal processing circuits without routing said data through any other intervening processing device between each respective ASIC device and the high bandwidth interconnection medium.

17. The reconfigurable communications infrastructure of claim 16, wherein each of said ASIC devices of said two or more signal processing circuits is an FPGA device.

18. The reconfigurable communications infrastructure of claim 17, wherein each given one of said FPGA devices of one of said signal processing circuits comprises user-defined circuitry coupled to said respective packet router of said given one of said FPGA devices;

and wherein said respective packet router of each given one of said FPGA devices of one of said signal processing circuits is configured to transmit and receive data packets between said user-defined circuitry of said given one of said FPGA devices of one of said signal processing circuits and an other one of said FPGA devices of an other different one of said signal processing circuits across said first and second common interfaces and through said high bandwidth interconnection medium.

19. The reconfigurable communications infrastructure of claim 17, wherein each given one of said FPGA devices of one of said signal processing circuits comprises at least one embedded processor coupled to said respective packet router of said given one of said FPGA devices;

and wherein said respective packet router of each given one of said FPGA devices of one of said signal processing circuits is configured to transmit and receive data packets between said at least one embedded processor of said given one of said FPGA devices of one of said signal processing circuits and an other one of said FPGA devices of an other different one of said signal processing circuits across said first and second common interfaces and through said high bandwidth interconnection medium.

20. The reconfigurable communications infrastructure of claim 17, wherein said reconfigurable communications infrastructure is a vehicle-based reconfigurable communications infrastructure comprising a vehicle;

and wherein each of said two or more signal processing circuits, first and second common interfaces, and said high bandwidth interconnection medium is positioned on or within said vehicle.

21. The reconfigurable communications infrastructure of claim 17, wherein said high bandwidth interconnection medium comprises an optical transmission medium.

22. The reconfigurable communications infrastructure of claim 17, wherein said high bandwidth interconnection medium comprises an interconnection medium having a data transmission capability of greater than or equal to about 1 Gbps.

23. The reconfigurable communications infrastructure of claim 17, wherein each of said signal processing circuits is a reconfigurable signal processing circuit that comprises two or more FPGA devices that each includes a packet router, said packet router of each one of said two or more FPGA devices of each given on of said signal processing circuits being coupled to each respective packet router of each of the other of said two or more FPGA devices of said same given one of said signal processing circuits;

and wherein said packet router of each given one of said two or more FPGA devices of said signal processing circuits is configured to communicate data packets within said given signal processing circuit by routing data packets to and from each other of said two or more FPGA devices of the same given one of said signal processing circuits without routing said data packets outside said given signal processing circuit across said first or second common interfaces to said high bandwidth interconnection medium.

24. The reconfigurable communications infrastructure of claim 23, wherein said packet router of each one of said two or more FPGA devices of each given one of said signal processing circuits is coupled to each respective packet router of each of the other of said two or more FPGA devices of same said same given one of said signal processing circuits by a separate respective duplex data communication link so as to form a direct serial interconnection between each two of said two or more FPGA devices of said same given one of said signal processing circuits;

and wherein said packet router of each given one of said two or more FPGA devices of each given one of said signal processing circuits is configured to communicate data packets within said given signal processing circuit by routing data packets to and from each other of said two or more FPGA devices of the same given one of said signal processing circuits without routing said data packets outside said given signal processing circuit across said first or second common interfaces to said high bandwidth interconnection medium.

25. The reconfigurable communications infrastructure of claim 17, wherein said two or more signal processing circuits are physically segregated from each other.

26. The reconfigurable communications infrastructure of claim 25, wherein said two or more signal processing circuits are physically segregated from each other by at least one of being positioned in different rooms of a given building or facility from each other, or being positioned in different compartments of a given mobile vehicle from each other.

27. A communications infrastructure, comprising two or more separate signal processing circuits, each one of said two or more signal processing circuits including multiple ASIC devices that each itself includes a packet router, said packet router of each one of said ASIC devices of each given one of said respective two or more signal processing circuits being coupled through respective first and second common interfaces and an intervening high speed serial optical link to a respective packet router of each of the ASIC devices of each other of said two or more signal processing circuits with no other processing device intervening between the high speed optical link and said ASIC devices of each of said two or more signal processing circuits.

28. The communications infrastructure of claim 27, wherein said interconnection further comprises a high bandwidth interconnection medium.

29. The communications infrastructure of claim 28, wherein each of said the ASIC devices of said two or more signal processing circuits is an FPGA device.

30. The communications infrastructure of claim 27, wherein said two or more signal processing circuits are physically segregated from each other by at least one of being positioned in different rooms of a given building or facility from each other, or being positioned in different compartments of a given mobile vehicle from each other.

31. A method, comprising:

providing two or more separate signal processing circuits, each one of said two or more signal processing circuits including multiple ASIC devices that each itself includes a packet router, said packet router of each one of said ASIC devices of each given one of said respective two or more signal processing circuits being coupled through respective first and second common interfaces and an intervening high speed serial optical link to a respective packet router of each of the other ASIC devices of each other of said two or more signal processing circuits with no other processing device intervening between the high speed serial optical link and said ASIC devices of each of said two or more signal processing circuits, and

selectively transferring at least one data packet from each said packet router of each one of said ASIC devices of each given one of said respective two or more signal processing circuits to each respective packet router of said at ASIC devices of each of the other of said two or more signal processing circuits through said first and second common interfaces and said intervening high speed serial optical link without routing said data through any other intervening processing device between each respective ASIC device and the high speed serial optical link.

32. The method of claim 31, wherein said two or more signal processing circuits are physically segregated from each other by at least one of being positioned in different rooms of a given building or facility from each other, or being positioned in different compartments of a given mobile vehicle from each other.

33. The method of claim 31, wherein said interconnection further comprises a high bandwidth interconnection medium.

34. The method of claim 33, wherein each of said ASIC devices of said two or more signal processing circuits is an FPGA device.