Methods of fabricating vertical JFET limited silicon carbide metal-oxide semiconductor field effect transistors

• US 7,923,320 B2
• Filed: 02/21/2007
• Issued: 04/12/2011
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Ryu, Sei-Hyung
• Primary Examiner(s): Gurley; Lynne A
• Assistant Examiner(s): YUSHINA, GALINA G
• Application Number:
  US11/677,422
• Publication Number:
  US 20070158658A1
• Time in Patent Office: 1,511 Days
• Field of Search: 257/77, 257/329, 257/330, 257/409, 257/350, 257/E21.054, 257/E21.065, 257/302, 257/E31.085, 438/206, 438/212
• US Class Current: 438/206
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. Methods of fabricating silicon carbide MOSFET devices are also provided.

Claims

1. A method of fabricating a silicon carbide metal-oxide semiconductor field effect transistor unit cell comprising:

providing an n-type silicon carbide drift layer;

providing a first p-type silicon carbide region adjacent the drift layer;

providing a first n-type silicon carbide region within the first p-type silicon carbide region;

providing an oxide layer adjacent the drift layer; and

providing an n-type silicon carbide limiting region between the drift layer and a portion of the first p-type silicon carbide region, wherein the n-type limiting region comprises a first portion laterally extending along a floor of the first p-type silicon carbide region and a second portion disposed adjacent to a sidewall of the first p-type silicon carbide region,

wherein the n-type limiting region has a carrier concentration that is greater than a carrier concentration of the drift layer, and wherein the first portion has a carrier concentration greater than a carrier concentration of the second portion.

2. A method according to claim 1, wherein providing a first p-type silicon carbide region further comprises:

implanting aluminum in the p-type silicon carbide region; and

annealing the p-type silicon carbide region at a temperature of at least 1500°

C.

3. A method according to claim 1, further comprising:

providing a gate contact on the oxide layer;

providing a source contact on the first n-type silicon carbide region; and

providing a drain contact on the drift layer opposite the oxide layer.

4. A method according to claim 1, wherein providing an n-type limiting region comprises:

providing an n-type epitaxial layer of silicon carbide on the n-type silicon carbide drift layer;

providing a mask on the epitaxial layer;

patterning the epitaxial layer to form the n-type limiting region.

5. A method according to claim 1, wherein providing an n-type limiting region comprises implanting n-type regions in the drift layer.

6. A method according to claim 1, wherein the n-type limiting region is formed to a thickness of from about 0.5 μ

m to about 1.5 μ

m and a carrier concentration of from about 1×

10¹⁵ to about 5×

10¹⁷ cm<sup>−

3</sup>.

7. A method according to claim 1, further comprising providing an n-type epitaxial layer on the first p-type region and a portion of the first n-type region, and between the first n-type region and the first p-type region and the oxide layer.

8. A method according to claim 1, further comprising providing a second p-type silicon carbide region within the first p-type silicon carbide region and adjacent the first n-type silicon carbide region.

9. A method according to claim 3, wherein the gate contact comprises polysilicon or metal.

10. A method according to claim 3, further comprising providing an n-type silicon carbide substrate between the drift layer and the drain contact.

11. A method according to claim 4, wherein providing a first p-type region comprises providing the first p-type region in but not through the epitaxial layer of silicon carbide.

12. The method of claim 1, wherein the first portion of the n-type limiting region is confined beneath the first p-type silicon carbide region.

13. A method of fabricating a silicon carbide metal-oxide semiconductor field effect transistor, comprising the steps of:

providing a drift layer of n-type silicon carbide;

providing first regions of p-type silicon carbide adjacent the drift layer;

providing a first region of n-type silicon carbide between peripheral edges of the first regions of p-type silicon carbide;

providing second regions of n-type silicon carbide in the first regions of p-type silicon carbide, wherein the second regions of n-type silicon carbide have a carrier concentration greater than a carrier concentration of the drift layer and are spaced apart from the peripheral edges of the first regions of p-type silicon carbide;

providing an oxide layer on the drift layer, the first region of n-type silicon carbide and the second regions of n-type silicon carbide; and

providing third regions of n-type silicon carbide laterally extending along respective floors of the first regions of p-type silicon carbide and between the first regions of p-type silicon carbide and the drift layer, wherein the first and third regions of n-type silicon carbide define an n-type limiting region having a carrier concentration greater than the carrier concentration of the drift layer, wherein the first region of n-type silicon carbide has a higher carrier concentration than a carrier concentration of the drift layer and has a lower carrier concentration than the carrier concentration of the third regions of n-type silicon carbide;

providing source contacts on portions of the second regions of n-type silicon carbide;

providing a gate contact on the oxide layer; and

providing a drain contact on the drift layer opposite the oxide layer.

14. A method according to claim 13, wherein providing third regions of n-type silicon carbide further comprises providing the third regions of n-type silicon carbide adjacent the peripheral edges of the first regions of p-type silicon carbide.

15. A method according to claim 13, further comprising providing an n-type silicon carbide epitaxial layer on the drift layer, wherein the first region of n-type silicon carbide and the third regions of n-type silicon carbide are formed from the epitaxial layer, and wherein the first regions of p-type silicon carbide are formed in the epitaxial layer.

16. A method according to Claim 13, wherein providing third regions of n-type silicon carbide comprises providing the third regions of n-type silicon carbide by implanting n-type regions in the drift layer.

17. A method according to claim 13, further comprising providing an n-type epitaxial layer of silicon carbide on the first p-type regions and the first region of n-type silicon carbide.

18. A method according to claim 13, further comprising providing an n-type silicon carbide layer between the drift layer and the drain contact, wherein the n-type silicon carbide layer has a higher carrier concentration than the carrier concentration of the drift layer.

19. A method according to claim 13, further comprising providing second p-type silicon carbide regions within the first p-type silicon carbide regions.

20. A method according to claim 13, wherein the third regions of n-type silicon carbide have a thickness of from about 0.5 μ

m to about 1.5 μ

m.

21. A method according to claim 13, wherein the third regions of n-type silicon carbide have a carrier concentration of from about 1×

10¹⁵ to about 5×

10¹⁷ cm<sup>−

3</sup>.

22. The method of claim 13, wherein the third regions of n-type silicon carbide are confined beneath the first regions of p-type silicon carbide.

23. A method according to claim 18, wherein the n-type silicon carbide layer comprises an n-type silicon carbide substrate.

24. A method of fabricating a silicon carbide metal-oxide semiconductor field effect transistor comprising:

providing an n-type silicon carbide drift layer;

providing spaced apart p-type silicon carbide well regions; and

providing an n-type silicon carbide limiting region between the well regions and the drift layer, wherein the n-type limiting region comprises a first portion laterally extending along respective floors of the well regions and a second portion adjacent to respective sidewalls of the well regions,

wherein the n-type limiting region has a carrier concentration higher than a carrier concentration of the drift layer, and wherein the first portion has a carrier concentration higher than a carrier concentration of the second portion.

25. A method according to claim 24, wherein providing an n-type limiting region comprises providing an epitaxial layer of silicon carbide on the drift layer, and wherein providing spaced apart p-type well regions comprises providing spaced apart p-type well regions in but not through the epitaxial layer.

26. The method of claim 24, wherein the first portion of the n-type limiting region is confined beneath the well regions.