Split gate non-volatile memory cell with improved endurance and method therefor

• US 7,923,328 B2
• Filed: 04/15/2008
• Issued: 04/12/2011
• Est. Priority Date: 04/15/2008
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: White, Ted R., Winstead, Brian A.
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US12/103,246
• Publication Number:
  US 20090256191A1
• Time in Patent Office: 1,092 Days
• Field of Search: 438/266, 438/260, 257/319, 257/E29.3, 257/E29.112, 257/E21.422, 257/E21.179
• US Class Current: 438/266
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A non-volatile memory cell including a substrate in which is formed a source region and a drain region defining a channel region between the source region and the drain region is provided. The non-volatile memory cell further includes a select gate structure overlying a first portion of the channel region. The non-volatile memory cell further includes a control gate structure formed overlying a second portion of the channel region, wherein the control gate structure includes a nanocrystal stack having a height, wherein the control gate structure has a convex shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure, wherein a ratio of radius of the control gate structure in the corner region to the height of the nanocrystal stack is at least 0.5.

Claims

1. A method of forming a non-volatile memory cell comprising:

forming a polysilicon layer overlying a first insulating layer formed over a substrate;

etching the polysilicon layer to form a select gate structure formed overlying the first insulating layer, wherein the select gate structure has at least one concave sidewall;

forming a second insulating layer over the select gate structure and overlying at least a portion of the substrate;

forming a layer of nanocrystals overlying at least a portion of the second insulating layer;

forming a third insulating layer overlying the layer of nanocrystals; and

forming a control gate structure adjacent to the select gate structure, wherein the control gate structure has a convex sidewall facing the at least one concave sidewall of the select gate structure, wherein the control gate structure includes a nanocrystal stack, and wherein a ratio of a radius of the convex sidewall in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the control gate structure to a height of the nanocrystal stack is at least 0.5.

2. The method of claim 1 further comprising forming a source region and a drain region on opposite sides of a channel region underlying the select gate structure and the control gate structure.

3. The method of claim 2, wherein the select gate structure overlies a first portion of the channel region, wherein the control gate structure overlies a second portion of the channel region, and wherein the first portion and the second portion overlap.

4. A method of forming a non-volatile memory cell comprising:

forming a polysilicon layer overlying a first insulating layer formed over a substrate;

etching the polysilicon layer to form an inverted-T select gate structure formed overlying the first insulating layer, wherein the inverted-T select gate structure has a concave shape in a corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a side surface of the inverted-T select gate structure;

forming a second insulating layer overlying the inverted-T select gate structure;

forming a layer of nanocrystals overlying at least a portion of the second insulating layer;

forming a third insulating layer overlying the layer of nanocrystals; and

forming a control gate structure adjacent to the inverted-T select gate structure, wherein the control gate structure has a convex shape facing the corner region.

5. The method of claim 4 further comprising forming a source region and a drain region on opposite sides of a channel region underlying the inverted-T select gate structure and the control gate structure.

6. The method of claim 5, wherein the inverted-T select gate structure overlies a first portion of the channel region, wherein the control gate structure overlies a second portion of the channel region, and wherein the first portion and the second portion overlap.

7. The method of claim 4, wherein the control gate structure includes a nanocrystal stack, and wherein a ratio of radius of the control gate structure in the corner region to a height of the nanocrystal stack is at least 0.5.

8. A method of forming a non-volatile memory cell comprising:

forming a polysilicon layer overlying a first insulating layer formed over a substrate;

etching the polysilicon layer to form a U-shaped polysilicon region, wherein the U-shaped polysilicon region has a concave shape in a first corner region formed at an intersection of a first plane substantially parallel to a top surface of the substrate and a second plane substantially parallel to a first inside surface of the U-shaped polysilicon region, and wherein the U-shaped polysilicon has a concave shape in a second corner region formed at an intersection of a third plane substantially parallel to the top surface of the substrate and a fourth plane substantially parallel to a second inside surface of the U-shaped polysilicon region;

etching a portion of the U-shaped polysilicon region to form a control gate region;

forming a second insulating layer overlying the control gate region and a remaining portion of the U-shaped polysilicon region;

forming a layer of nanocrystals overlying at least a portion of the second insulating layer;

forming a third insulating layer overlying the layer of nanocrystals; and

forming a first select gate structure, a second select gate structure, a first control gate structure adjacent to the first select gate structure, and a second control gate structure adjacent to the second select gate structure, wherein the first control gate structure has a convex shape facing the first corner region, and the second control gate structure has a convex shape facing the second corner region.

9. The method of claim 8 further comprising forming a common source/drain region.

10. The method of claim 8, wherein each of the first control gate structure and the second control gate structure includes a nanocrystal stack, and wherein a first ratio of a radius of the first control gate structure in the first corner region to a height of the nanocrystal stack is at least 0.5, and wherein a second ratio of a radius of the second control gate structure in the second corner region to the height of the nanocrystal stack is at least 0.5.