Digital isolator with communication across an isolation barrier

• US 7,923,710 B2
• Filed: 03/08/2007
• Issued: 04/12/2011
• Est. Priority Date: 03/08/2007
• Status: Active Grant

• Current Assignee: Kinetic Technologies International Holdings LP
• Original Assignee: Akros Silicon, Inc. (Kinetic Technologies Incorporated)
• Inventors: Camagna, John R., Ghoshal, Sajol, Crawley, Philip John
• Primary Examiner(s): Sohn; Seung C
• Application Number:
  US11/683,985
• Publication Number:
  US 20080218258A1
• Time in Patent Office: 1,496 Days
• Field of Search: 250/551, 375/316, 375/244
• US Class Current: 250/551
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2200/271 the DC-isolation amplifier, e.g. chopper amplifier, modulation/demodulation amplifier, uses capacitive isolation means, e.g. capacitors
• CPC Class Codes: H03F 2203/45101 Control of the DC level being present
• CPC Class Codes: H03F 3/393 with field-effect devices
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

A signal isolator comprises an isolation barrier, a transmitter, a differentiator, and a recovery circuit. The transmitter is coupled to a first side of the isolation barrier and is configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge. The differentiator is coupled to a second side that is isolated from the first side of the isolation harrier and differentiates the differential signal. The recovery circuit is coupled to the differentiator and operates to recover an output information signal based on the information in the single transition edge.

Claims

1. A method for transmitting an information signal from a first side to a second side of an isolation barrier comprising:

receiving the information signal at the first side;

encoding a differential signal from the information signal as a transition that contains all information in a single transition edge;

passing the differential signal to the second side of the isolation barrier;

differentiating the passed signal on the second side of the isolation barrier; and

recovering an output information signal on the second side of the isolation barrier based on the information in the single transition edge.

2. The method according to claim 1 further comprising:

recovering the output information signal on the second side of the isolation barrier using positive feedback.

3. The method according to claim 1 further comprising:

passing the differential signal across a capacitive isolation barrier.

4. The method according to claim 1 further comprising:

passing the differential signal across an inductive isolation barrier.

5. The method according to claim 1 further comprising:

differentiating the passed signal whereby a common-mode-to-differential component is separated from true differential components.

6. The method according to claim 1 further comprising:

differentiating the passed signal in a single stage; and

maintaining differentiation in a linear range by common mode suppression.

7. The method according to claim 1 further comprising:

differentiating the passed signal in multiple stages whereby linear differentiation is maintained without common mode suppression.

8. A method for transmitting an information signal from a first side to a second side of an isolation barrier comprising:

receiving a logic signal with first and second transition edges that shift the logic signal between two states;

communicating a differential signal across an isolation barrier that contains all information in the logic signals in a single transition edge;

differentiating the communicated differential signal; and

recovering a signal indicative of the first and second transition edges from the differentiated signal.

9. The method according to claim 8 further comprising:

communicating the differential signal across the isolation barrier on a fully differential pathway.

10. A method for transmitting a signal from a transmitting circuit across an isolation barrier to a receiving circuit comprising:

converting an information signal to a digital signal that contains all information in the information signal in a single transition edge;

passing the digital signal across the isolation barrier;

differentiating the passed digital signal; and

recovering an output information signal from the differentiated digital signal based on the information in the single transition edge.

11. The method according to claim 10 further comprising:

recovering the output information signal using positive feedback.

12. A method for constructing a signal isolator comprising:

forming first and second separate dies from a common wafer; and

forming a transmitter on the first die and a receiver on the second die in a configuration that communicates an information signal across an isolation barrier as a digital signal that contains all information in a single transition edge.

13. The method according to claim 12 further comprising:

forming the transmitter and the receiver wherein the first and second dies are matched and communication correctness is ensured.

14. The method according to claim 12 further comprising:

forming oscillators that are matched to a selected tolerance on the first and second dies.

15. The method according to claim 14 further comprising:

configuring the oscillators to communicate information across the isolation barrier by frequency modulation.

16. The method according to claim 12 further comprising:

forming the first and second separate dies from adjacent positions on the common wafer.

17. The method according to claim 12 further comprising:

forming at least two transmitter-receiver channels in the first and second separate dies in a configuration that enables comparison of communication signals between channels and correction of corrupted edge transmission.

18. A method for operating a signal isolator comprising:

providing first and second separate dies from a common wafer comprising a transmitter on the first die and a receiver on the second die in a configuration that communicates an information signal across an isolation barrier as a digital signal that contains all information in a single transition edge, and oscillators that are matched to a selected tolerance on the first and second dies;

determining frequency of a signal transmitted across the isolation barrier;

comparing frequency of a local oscillator signal to the frequency of the transmitted signal; and

correcting transmitted state based on the comparison.

19. A signal isolator comprising:

an isolation barrier;

a transmitter coupled to a first side of the isolation barrier and configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge;

a differentiator coupled to a second side isolated from the first side of the isolation barrier that differentiates the differential signal; and

a recovery circuit coupled to the differentiator and configured to recover an output information signal based on the information in the single transition edge.

20. The signal isolator according to claim 19 further comprising:

the recovery circuit configured to recover the output information signal using positive feedback.

21. The signal isolator according to claim 19 further comprising:

the differentiator configured to separate a common-mode-to-differential signal component from true differential signal components.

22. The signal isolator according to claim 19 further comprising:

the differentiator configured as a current mode differentiator.

23. The signal isolator according to claim 19 further comprising:

a common mode suppression control circuit coupled to the differentiator and configured to maintain the differentiator in a linear range.

24. The signal isolator according to claim 19 further comprising:

a plurality of differentiators coupled to the second side of the isolation barrier and configured to separate a common mode error signal from differential.

25. The signal isolator according to claim 19 further comprising:

the recovery circuit comprising a comparator coupled to the differentiator and a feedback device coupled to the comparator.

26. The signal isolator according to claim 19 further comprising:

the recovery circuit comprising a peak detector coupled to the differentiator and a feedback device coupled to the peak detector.

27. A signal isolator comprising:

an integrated circuit substrate;

an isolation barrier formed by at least two interlayer metal dielectric capacitors that isolates a first domain from a second domain in the substrate;

a transmitter in the first domain coupled to the isolation barrier and configured to transmit an information signal through the isolation barrier;

a differentiator in the second domain coupled to the isolation barrier and configured to differentiate the transmitted information signal; and

a recovery circuit in the second domain coupled to the differentiator and configured to recover an output information signal based on the differentiated information signal.

28. The signal isolator according to claim 27 further comprising:

the recovery circuit configured to recover the output information signal using positive feedback.

29. The signal isolator according to claim 27 further comprising:

the isolation barrier forming a differential transmission pathway comprising a plurality of differential lines each comprising a plurality of parallel capacitive pathways configured to create magnetic and electrical differentiality.

30. The signal isolator according to claim 27 further comprising:

the differential transmission pathway comprising first and second differential lines, each differential line comprising two parallel pathways, each pathway comprising first and second capacitors coupled at a bond pad.

31. The signal isolator according to claim 30 further comprising:

the bond pads arranged in positions attaining first-order common-centroiding of the capacitors.

32. The signal isolator according to claim 27 further comprising:

the isolation barrier configured in an arrangement selected from arrangements comprising the at least two interlayer metal dielectric capacitors formed in the first domain, the at least two interlayer metal dielectric capacitors formed in the second domain, the at least two interlayer metal dielectric capacitors formed partly in the first domain and partly in the second domain, the at least two interlayer metal dielectric capacitors formed between the first and second domains, and the at least two interlayer metal dielectric capacitors formed partly in the first domain, partly in the second domain, and partly between the first and second domain.

33. The signal isolator according to claim 27 further comprising:

the differentiator configured as a current mode differentiator.

34. A signal isolator comprising:

an isolation barrier forming a differential transmission pathway comprising a plurality of differential lines each comprising a plurality of parallel capacitive pathways configured to create magnetic and electrical differentiality;

a transmitter coupled to a first side of the isolation barrier and configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge; and

a recovery circuit coupled to the differentiator and configured to recover an output information signal based on the information in the single transition edge.

35. The signal isolator according to claim 34 further comprising:

a differentiator coupled to a second side isolated from the first side of the isolation barrier that differentiates the differential signal.

36. The signal isolator according to claim 34 further comprising:

the differential transmission pathway comprising first and second differential lines, each differential line comprising two parallel pathways, each pathway comprising first and second capacitors coupled at a bond pad.

37. The signal isolator according to claim 34 further comprising:

a common mode suppression circuit coupled between the isolation barrier and the recovery circuit, the common mode suppression circuit configured to maintain differentiation in a linear range.

38. The signal isolator according to claim 34 further comprising:

the differentiator configured as a current mode differentiator.

39. A signal isolator comprising:

an isolation barrier;

a modulator coupled to an input side of the isolation barrier configured to receive a logic signal with first and second transition edges that shift the logic signal between two states, convert the logic signal to a differential signal, and pass the differential signal across the isolation barrier;

a differentiator coupled to an output side of the isolation barrier that differentiates the communicated differential signal; and

a recovery circuit coupled to the differentiator that recovers a signal indicative of the first and second transition edges from the differentiated signal.

40. The signal isolator according to claim 39 further comprising:

the recovery circuit configured to recover the output information signal using positive feedback.

41. The signal isolator according to claim 39 further comprising:

the modulator configured to create the differential signals that contains all information in the logic signals in a single transition edge.

42. The signal isolator according to claim 39 further comprising:

a differential comparator comprising the modulator.

43. The signal isolator according to claim 39 further comprising:

a differential comparator coupled to a set/reset latch comprising the recovery circuit.

44. The signal isolator according to claim 39 further comprising:

a powered system on the input side of the isolation barrier and an isolated system on the output side of the isolation barrier.

45. The signal isolator according to claim 39 further comprising:

the differentiator configured as a current mode differentiator.

46. A signal isolator comprising:

an isolation barrier isolating first and second domains;

a modulator in the first domain coupled to the isolation barrier configured to convert an information signal to a digital signal that contains all information in the information signal in an edge of a single transition and passes the digital signal across the isolation barrier to the second domain;

a differentiator in the second domain coupled to the isolation barrier that differentiates the passed digital signal; and

a recovery circuit in the second domain coupled to the differentiator and configured to recover an output information signal from the differentiated digital signal based on the information in the single transition edge.

47. The signal isolator according to claim 46 further comprising:

a powered system in the first domain and an isolated system in the second domain.

48. A signal isolator comprising:

an isolation barrier isolating first and second domains;

at least one fully differential transmitter in the first domain coupled to the isolation barrier configured to transmit a digital signal containing all information in an information signal in an edge of a single transition across the isolation barrier to the second domain; and

at least one fully differential receiver in the second domain coupled to the isolation barrier configured to receive and differentiate the transmitted digital signal.

49. A signal isolator comprising:

an isolation barrier;

first and second separate dies from a common wafer comprising a transmitter on the first die and a receiver on the second die in a configuration that communicates an information signal across the isolation barrier as a digital signal that contains all information in a single transition edge; and

oscillators on the first and second dies that are matched to a selected tolerance.

50. The signal isolator according to claim 49 further comprising:

a state machine coupled to the receiver on the second die; and

a failsafe logic coupled to the state machine on the second die, the state machine and the failsafe logic configured to determine frequency of a signal transmitted across the isolation barrier, compare frequency of a local oscillator signal to the frequency of the transmitted signal, and correct transmitted state based on the comparison.