Thin film transistors and methods of manufacturing the same

• US 7,923,722 B2
• Filed: 12/03/2007
• Issued: 04/12/2011
• Est. Priority Date: 05/29/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Kyung-seok, Ryu, Myung-kwan, Jung, Ji-sim, Kim, Tae-sang, Park, Kyung-bae, Kwon, Jang-yeon
• Primary Examiner(s): Nguyen; Thinh T
• Application Number:
  US11/987,610
• Publication Number:
  US 20080296568A1
• Time in Patent Office: 1,226 Days
• Field of Search: 257/43, 257/E29.068, 257/E21.46, 438/85, 438/86, 438/104, 438/754
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A TFT includes a zinc oxide (ZnO)-based channel layer having a plurality of semiconductor layers. An uppermost of the plurality of semiconductor layers has a Zn concentration less than that of a lower semiconductor layer to suppress an oxygen vacancy due to plasma. The uppermost semiconductor layer of the channel layer also has a tin (Sn) oxide, a chloride, a fluoride, or the like, which has a relatively stable bonding energy against plasma. The uppermost semiconductor layer is relatively strong against plasma shock and less decomposed when being exposed to plasma, thereby suppressing an increase in carrier concentration.

Claims

1. A thin film transistor (TFT) comprising:

a channel layer formed on a substrate, the channel layer including a plurality of stacked zinc oxide (ZnO)-based semiconductor layers, an uppermost of the plurality of semiconductor layers having a Zn concentration less than at least one other semiconductor layer;

a gate disposed between the substrate and the channel layer;

a gate insulating layer disposed between the channel layer and the gate; and

a source electrode and a drain electrode disposed on respective sides of the channel layer.

2. The TFT of claim 1, wherein the uppermost semiconductor layer of the channel layer includes a tin (Sn) oxide.

3. The TFT of claim 1, wherein the channel layer is formed of gallium-indium-zinc-oxide (GIZO).

4. The TFT of claim 3, wherein the uppermost semiconductor layer of the channel layer includes a chloride or a fluoride.

5. The TFT of claim 1, wherein the uppermost semiconductor layer of the channel layer includes a chloride.

6. The TFT of claim 5, wherein the uppermost semiconductor layer includes at least one selected from the group consisting of GaCl_x, InCl_x and ZnCl_y, where 0<

x≦

3 and 0<

y≦

2.

7. The TFT of claim 6, wherein the uppermost semiconductor layer includes at least one selected from the group consisting of GaCl₃, InCl₃ and ZnCl₂.

8. The TFT of claim 1, wherein the channel layer is a a(In₂O₃).b(Ga₂O₃).c(ZnO) layer, where a, b, and c are real numbers satisfying a≧

0, b≧

0 and c>

0.

9. The TFT of claim 8, wherein a≧

1, b≧

1, and 0<

c≦

1.

10. The TFT of claim 1, wherein the uppermost semiconductor layer includes a fluoride.

11. The TFT of claim 10, wherein the uppermost semiconductor layer of the channel layer includes at least one selected from the group consisting of GaF_x, InF_x, ZnF_y, where 0<

x≦

3 and 0<

y≦

2.

12. The TFT of claim 11, wherein the uppermost semiconductor layer of the channel layer includes at least one of GaF₃, InF₃, and ZnF₂.

13. The TFT of claim 1, further including,

a passive layer covering the channel layer, the source electrode, and the drain electrode.