Metal gate semiconductor device and manufacturing method

• US 7,923,759 B2
• Filed: 04/10/2006
• Issued: 04/12/2011
• Est. Priority Date: 03/25/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Kuang-Hsin, Yang, Fu-Liang, Huang, Chien-Chao
• Primary Examiner(s): Nguyen; Thinh T
• Application Number:
  US11/400,853
• Publication Number:
  US 20060202237A1
• Time in Patent Office: 1,828 Days
• Field of Search: 257/250, 257/296, 257/388, 257/412, 257/413, 257/E29.156, 438/302
• US Class Current: 257/250
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

Claims

1. A semiconductor device comprising:

a substrate;

a plurality of first gate electrodes located on the substrate;

a first gate dielectric located between each first gate electrode and the substrate, the first gate dielectrics being substantially the same thickness;

at least one of the first gate electrodes made of a first material;

at least one of the first gate electrodes made of a second material which is different from the first material;

at least one second gate electrode located on the substrate, the at least one second gate electrode being made of either the first material or the second material; and

a second gate dielectric located between each at least one second gate electrode and the substrate, the second gate dielectrics having a thickness different from that of the first gate dielectrics.

2. The semiconductor device of claim 1 wherein the substrate is silicon on insulator.

3. The semiconductor device of claim 1 wherein the first material is polysilicon.

4. The semiconductor device of claim 1 wherein the second material is selected from the group consisting of a metal, a metal alloy, a metal silicide, and a combination thereof.

5. The semiconductor device of claim 1 wherein the second material includes a plurality of materials.

6. The semiconductor device of claim 1 wherein at least one gate dielectric is an oxide.

7. The semiconductor device of claim 1 wherein at least one gate dielectric is a high K material.

8. A semiconductor device comprising:

a substrate;

a metal gate electrode located on the substrate and having a top surface portion and a side surface portion; and

a plurality of spacers, the plurality of spacers including a first spacer adjacent to the metal gate electrode and engaging the top surface portion and the side surface portion of the metal gate electrode, and including a second spacer adjacent to the first spacer;

wherein the metal gate electrode is a metal silicide.

9. The semiconductor device of claim 8 wherein the first spacer or second spacer is selected from the group consisting of SiON, Si₃N₄, SiC, and a combination thereof.

17. The semiconductor device of claim 8,

wherein the metal gate electrode includes a further side surface portion, the side surface portions being on opposite sides of the metal gate electrode and facing away from each other;

and

wherein the first spacer engages the top surface portion and both side surface portions of the metal gate electrode.

10. A semiconductor device comprising:

a substrate;

a gate electrode located on the substrate;

a first spacer surrounding the gate electrode and spaced apart from the gate electrode to form a first region therebetween; and

a second spacer located both inside and outside of the first region.

11. The semiconductor device of claim 10 wherein the gate electrode is a metal silicide.

12. The semiconductor device of claim 10 wherein the first spacer or second spacer is selected from the group consisting of SiON, Si₃N₄, SiC, and a combination thereof.

18. The semiconductor device of claim 10 wherein the second spacer engages both a surface portion of the first spacer facing the first region and a surface portion of the first spacer facing away from the first region.

13. A semiconductor device comprising:

a substrate;

a gate electrode located on the substrate;

a first spacer located on the substrate and adjacent to the gate electrode;

a second spacer located adjacent the first spacer, which surrounds the gate electrode and is spaced apart from the gate electrode to form a first region therebetween; and

a third spacer located both inside and outside of the first region.

14. The semiconductor device of claim 13 wherein the gate electrode is a metal silicide.

15. The semiconductor device of claim 13 wherein the first spacer is SiO₂.

16. The semiconductor device of claim 13 wherein the second spacer or third spacer is selected from the group consisting of SiON, Si₃N₄, SiC, and a combination thereof.

19. The semiconductor device of claim 13 wherein the third spacer engages both a surface portion of the second spacer facing the first region and a surface portion of the second spacer facing away from the first region.

20. The semiconductor device of claim 13 wherein the entirety of the second spacer is vertically higher than the first spacer.