Planar microshells for vacuum encapsulated devices and damascene method of manufacture

• US 7,923,790 B1
• Filed: 03/09/2007
• Issued: 04/12/2011
• Est. Priority Date: 03/09/2007
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Monadgemi, Pezhman, Howe, Roger T., Quevy, Emmanuel P.
• Primary Examiner(s): Huynh; Andy
• Application Number:
  US11/716,070
• Time in Patent Office: 1,495 Days
• Field of Search: 257/414, 257/415, 257/416, 257/417, 257/E23.193, 438/48, 438/49, 438/53, 438/125, 438/126, 438/127
• US Class Current: 257/415
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00293 maintaining a controlled atmosphere with processes not provided for in B81C1/00285
• CPC Class Codes: B81C 2203/0136 Growing or depositing of a covering layer
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: B81C 2203/0721 Forming the micromechanical structure with a low-temperature process B81C2203/0735 takes precedence
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure

Abstract

Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell.

Claims

1. A microshell comprising:

a perforated pre-sealing layer to partially enclose a chamber on a substrate, the perforated pre-sealing layer including at least one perforation defined therein that is offset in position from a released MEMS structure enclosed within the chamber; and

a sealing layer on the pre-sealing layer to close the perforation, wherein the sealing layer further comprises;

a non-hermetic occluding layer to occlude the perforation; and

a metal hermetic layer to seal the perforation.

2. The microshell of claim 1, wherein the pre-sealing layer contacts a MEMS structural element to provide asymmetrical anchoring to the released MEMS structure.

3. The microshell of claim 1, wherein the pre-sealing layer contacts a plurality of MEMS resonant members within the microshell to mechanically couple the plurality.

4. The microshell of claim 1, wherein the pre-sealing layer includes a plurality of perforations defined therein, with adjacent perforations of the plurality of perforations defined in the pre-sealing layer being offset relative to each other to form a staggered perforation pattern that is defined in the pre-sealing layer.

5. The microshell of claim 1, wherein the microshell has a sidewall;

and wherein the pre-sealing layer forms at least a portion of the sidewall of the chamber.

6. The microshell of claim 1, wherein the pre-sealing layer further comprises a gas permeable layer.

7. The microshell of claim 6, wherein the gas permeable layer is an oxide of silicon.

8. The microshell of claim 1, wherein the occluding layer comprises a dielectric.

9. The microshell of claim 8, wherein the dielectric is an oxide of silicon.

10. The microshell of claim 1, wherein the hermetic layer comprises aluminum.

11. The microshell of claim 1, wherein the microshell has an outer sidewall;

and wherein the hermetic layer is electrically coupled to a conductive layer extending down the outer sidewall of the microshell.

12. The microshell of claim 11, wherein the conductive layer is electrically coupled to a ground ring to electrically ground the microshell.

13. The microshell of claim 12, wherein the sealing layer comprises a semiconductor layer over the hermetic layer to reinforce the shell.

14. The microshell of claim 13, wherein the semiconductor layer comprises an alloy of silicon and germanium to form a germanosilicide with the hermetic layer.

15. The microshell of claim 1, wherein the perforation has an aspect ratio greater than 8:

1 height to width ratio.

16. The microshell of claim 15, wherein the perforation is above the chamber.

17. A method of forming a microshell comprising:

forming a non-planar sacrificial layer over a substrate and over a structural component of a MEMS;

forming a pre-sealing layer over the non-planar sacrificial layer;

planarizing the pre-sealing layer to perforate the pre-sealing layer with a topographic feature of the non-planar sacrificial layer to form a perforated pre-sealing layer including at least one perforation defined therein that is offset in position from the MEMS structure;

removing the non-planar sacrificial layer through the perforation to release the structural component of a MEMS within a chamber and form the chamber around the MEMS structure under the pre-sealing layer, the perforated pre-sealing layer including at least one perforation defined therein that is offset in position from the released MEMS structure enclosed within the chamber; and

sealing the per-sealing layer with a sealing layer on the pre-sealing layer to close the perforation, wherein the sealing layer comprises;

a non-hermetic occluding layer to occlude the perforation, and

a metal hermetic layer to seal the perforation.

18. The method of claim 17, wherein the sacrificial material is formed of the same material as a release layer surrounding the structural component.

19. The method of claim 18, wherein forming the sacrificial material further comprises depositing the sacrificial material at a temperature below 450°

C.

20. The method of claim 19, wherein forming the sacrificial material further comprises depositing germanium.

21. The method of claim 20, wherein forming the sacrificial material further comprises depositing an etch stop layer between a first and second layer of germanium.

22. The method of claim 17, wherein forming the non-planar sacrificial layer further comprises:

forming a sacrificial material over the substrate;

etching the sacrificial material with a first mask to define an edge of the chamber;

etching the sacrificial material with a second mask to form an isolated sacrificial layer having a blade of sacrificial material extending upwards from the substrate.

23. The method of claim 22, wherein the second mask defines staggered rows of blades to form a crenelated sacrificial layer such that planarizing the pre-sealing layer perforates the pre-sealing layer to define a plurality of perforations therein, with adjacent perforations of the plurality of perforations defined in the pre-sealing layer being offset relative to each other to form a staggered perforation pattern that is defined in the pre-sealing layer.

24. The method of claim 22, wherein the sacrificial material is etched to have a sloped blade profile.

25. The method of claim 22, wherein forming the pre-sealing layer over the non-planar sacrificial layer further comprises depositing a dielectric pre-sealing layer over the non-planar sacrificial layer to cover the blade and chamber edge.

26. The method of claim 22, wherein forming the pre-sealing layer over the non-planar sacrificial layer further comprises depositing a getter layer over the non-planar sacrificial layer to cover the blade.

27. The method of claim 22, wherein forming the pre-sealing layer over the non-planar sacrificial layer further comprises depositing over the non-planar sacrificial layer a first dielectric layer and a second dielectric layer with a getter layer there between.

28. The method of claim 22, further comprising forming the microshell to have an outer sidewall and a conductive layer extending down the outer sidewall of the microshell;

and forming the hermetic layer to be electrically coupled to the conductive layer extending down the outer sidewall of the microshell.

29. The method of claim 22, wherein the non-planar sacrificial layer is removed with hydrogen peroxide.

30. The method of claim 17, wherein sealing the pre-sealing layer further comprises:

nonconformally depositing a dielectric to physically occlude the perforation; and

depositing a metal to hermetically seal the perforated pre-sealing layer.

31. The method of claim 30, wherein the chamber is heated for at least 30 seconds to a temperature above 400°

C. before depositing the dielectric to desorb contaminants.

32. The method of claim 30, wherein the dielectric is deposited with the substrate tilted by a small angle relative to a predominant material flux within the deposition chamber to reduce back-deposition of the sealing material.

33. The method of claim 17, further comprising:

etching through the sealing layer to expose a metal ground ring adjacent to the chamber; and

depositing a conductive layer on the sealing layer and ground ring to electrically ground the microshell.

34. The method of claim 17, further comprising:

depositing a semiconductor over the conductive layer to structurally reinforce the microshell.

35. The method of claim 34, wherein the semiconductor comprises germanium to form a germanosilicide.

36. An apparatus comprising:

a grounded metal-insulator microshell comprising;

a perforated pre-sealing layer to partially enclose a chamber on a substrate, the perforated pre-sealing layer including at least one perforation defined therein that is offset in position from a released MEMS structure enclosed within the chamber;

a non-hermetic occluding layer to occlude the perforation;

a metal hermetic sealing layer on the pre-sealing layer to close the perforation; and

on the sealing layer, a conductive layer electrically coupled to a ground ring adjacent to the metal-insulator microshell; and

a released interconnect structure encapsulated by the grounded metal-insulator microshell.

37. The apparatus of claim 36, further comprising a CMOS device on the substrate electrically coupled to the released interconnect structure.

38. The apparatus of claim 37, wherein the released interconnect structure is a MEMS resonator.

39. The apparatus of claim 37, wherein the CMOS device is a timing circuit including a voltage controlled oscillator and a phase-lock loop.

40. The apparatus of claim 36, wherein the released interconnect structure forms a one-port capacitor with the grounded metal-insulator microshell.

41. The apparatus of claim 36, wherein the released interconnect structure forms an inductor.

42. The apparatus of claim 36, wherein the released interconnect structure forms a microstrip or coplanar waveguide transmission line.

43. A microshell comprising:

a perforated pre-sealing layer to partially enclose a chamber on a substrate; and

a sealing layer on the pre-sealing layer to close a perforation, wherein the sealing layer further comprises;

a non-hermetic occluding layer to occlude the perforation; and

a metal hermetic layer to seal the perforation;

wherein the microshell has an outer sidewall; and

wherein the hermetic layer is electrically coupled to a conductive layer extending down the outer sidewall of the microshell.

44. The microshell of claim 43, wherein the conductive layer is electrically coupled to a ground ring to electrically ground the microshell.

45. The microshell of claim 44, wherein the sealing layer comprises a semiconductor layer over the hermetic layer to reinforce the shell.

46. The microshell of claim 45, wherein the semiconductor layer comprises an alloy of silicon and germanium to form a germanosilicide with the hermetic layer.

47. The microshell of claim 43, wherein the pre-sealing layer includes a plurality of perforations defined therein, with adjacent perforations of the plurality of perforations defined in the pre-sealing layer being offset relative to each other to form a staggered perforation pattern that is defined in the pre-sealing layer.

48. The microshell of claim 43, wherein the microshell has a sidewall;

and wherein the pre-sealing layer forms at least a portion of the sidewall of the chamber.

49. The microshell of claim 43, wherein the pre-sealing layer further comprises a gas permeable layer.

50. The microshell of claim 49, wherein the gas permeable layer is an oxide of silicon.

51. The microshell of claim 43, wherein the occluding layer comprises a dielectric.

52. The microshell of claim 51, wherein the dielectric is an oxide of silicon.

53. The microshell of claim 43, wherein the hermetic layer comprises aluminum.

54. A microshell comprising:

a perforated pre-sealing layer to partially enclose a chamber on a substrate; and

a sealing layer on the pre-sealing layer to close a perforation, wherein the sealing layer further comprises;

a non-hermetic occluding layer to occlude the perforation; and

a metal hermetic layer to seal the perforation;

wherein the pre-sealing layer includes a plurality of perforations defined therein, with adjacent perforations of the plurality of perforations defined in the pre-sealing layer being offset relative to each other to form a staggered perforation pattern that is defined in the pre-sealing layer.