DRAM having deep trench capacitors with lightly doped buried plates

• US 7,923,815 B2
• Filed: 01/07/2008
• Issued: 04/12/2011
• Est. Priority Date: 01/07/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Faltermeier, Johnathan E., Cheng, Kangguo, Wang, Geng, Parries, Paul C.
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Patton; Paul E
• Application Number:
  US11/969,986
• Publication Number:
  US 20090174031A1
• Time in Patent Office: 1,191 Days
• Field of Search: 257/301, 257/E21.396, 257/532, 257/E29.342, 257/E29.346, 438/243, 438/149, 438/386, 438/389, 438/246
• US Class Current: 257/532
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

Claims

1. A microelectronic element comprising:

a semiconductor substrate;

a first capacitor comprising a trench formed in the substrate, a first buried plate surrounding the trench, a node dielectric lining the trench, and a node disposed within the trench, and wherein the first buried plate has a first doping concentration;

a second capacitor comprising a trench formed in the substrate, a second buried plate surrounding the trench, a node dielectric lining the trench, and a node disposed within the trench, and wherein the second buried plate has a second doping concentration;

a first contact plug directly connected to the first buried plate for applying a first bias voltage to the first buried plate;

a second contact plug directly connected to the second buried plate for applying a second bias voltage, different than the first bias voltage, to the second buried plate; and

the semiconductor substrate having a non-uniform doping concentration wherein the first doping concentration differs from the second doping concentration by at least one order of magnitude.

2. The microelectronic element of claim 1, wherein:

the first doping concentration is between 1E13 and 1E18 atoms per cubic centimeter, and

wherein the second doping concentration is greater than 1E19 atoms per cubic centimeter.

3. The microelectronic element of claim 2, wherein:

the first doping concentration is less than 1E17 atoms per cubic centimeter.

4. The microelectronic element of claim 3, wherein:

the first doping concentration is between 1E13 and 1E18 atoms per cubic centimeter.

5. The microelectronic element of claim 2, wherein:

the second doping concentration is between 1E19 and 1E20 atoms per cubic centimeter.

6. The microelectronic element of claim 3, wherein:

the first doping concentration is between 1E17 and 1E18 atoms per cubic centimeter.

7. The microelectronic element of claim 1, wherein:

the capacitance of the first capacitor is at least 2.0 times the capacitance of the second capacitor.

8. The microelectronic element of claim 1, wherein:

the capacitance of the first capacitor is at least 1.2 times the capacitance of the second capacitor.

9. The microelectronic element of claim 1, wherein:

a voltage difference between the biases of the buried plates of the first capacitor and the second capacitor is at least 0.5V; and

the capacitance of the first capacitor at least 1.2 times the capacitance of the second capacitor.

10. The microelectronic element of claim 1, wherein:

the first and second capacitors are deep trench capacitors and are separated from one another by a layer of isolation disposed on the surface of the substrate.

11. The microelectronic element of claim 1, wherein:

the first and second capacitors are storage capacitors of DRAM/eDRAM cells.