Semiconductor device, and design method, inspection method, and design program therefor

• US 7,924,042 B2
• Filed: 08/24/2006
• Issued: 04/12/2011
• Est. Priority Date: 11/01/2002
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: Umc Japan
• Inventors: Isobe, Shinobu
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Vazquez; Arleen M
• Application Number:
  US11/509,270
• Publication Number:
  US 20060288324A1
• Time in Patent Office: 1,692 Days
• Field of Search: 324754-758, 324/765, 174/255, 174/262, 361/795, 361/799
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308

Abstract

A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Claims

1. An inspection method of inspecting a multilayer semiconductor device which includes a plurality of circuit blocks which include individual functions of the semiconductor device and are formed on a semiconductor substrate, the method comprising the step of:

performing inspection with an electrode of a measurement terminal, wherein the measurement terminal is provided on a wiring line which extends from one of the plurality of circuit blocks which include the individual functions of the semiconductor device, the electrode being formed in an uppermost layer of the semiconductor device, and the measurement terminal including a pad in each remaining layer of the semiconductor device, and pads in each remaining layer of the semiconductor device being electrically connected with each other by contact holes which pass through each insulating film of the semiconductor device.

2. The inspection method as claimed in claim 1, wherein the step of performing inspection includes measuring at least one of a voltage and a logic state of the wiring line on which the measurement terminal is provided, by one of contacting the electrode of the measurement terminal with a probe and irradiating the electrode with an electron beam.

3. A multilayer semiconductor device which includes a plurality of circuit blocks which include individual functions of the semiconductor device, the circuit blocks being formed on a semiconductor substrate, wherein the semiconductor device is inspected the inspection method in accordance with claim 1, the semiconductor device comprising:

measurement terminals, each provided on the wiring line which extends from one of the plurality of circuit blocks which include the individual functions of the semiconductor device, wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device and a pad provided in each remaining layer of the semiconductor device, and the electrode and the pads are connected with each other by the contact holes.

4. The multilayer semiconductor device as claimed in claim 3, wherein positions of the electrode and the pad provided in each remaining layer are substantially the same in plan view.