System and method of altering a PWM carrier power spectrum

• US 7,924,200 B2
• Filed: 09/30/2010
• Issued: 04/12/2011
• Est. Priority Date: 04/01/2008
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Khoury, John M
• Primary Examiner(s): Jeanglaude; Jean B
• Application Number:
  US12/895,804
• Publication Number:
  US 20110019728A1
• Time in Patent Office: 194 Days
• Field of Search: 341/152, 375/238, 381/104, 455/127.3
• US Class Current: 341/152
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

In a particular embodiment, a circuit device includes an input to receive a pulse-width modulated (PWM) signal and an output to send a modulated PWM signal. The circuit device further includes a pulse edge control circuit coupled between the input and the output. The pulse edge control circuit receives the PWM signal via the input and includes a control input to receive a modulation control signal. The pulse edge control circuit is adapted to modify the PWM signal to provide the modulated PWM signal with suppressed carrier power and associated harmonics to the output based on the modulation control signal. The circuit device further includes a modulation sequence controller adapted to provide the modulation control signal via the control input. The modulation control signal selectively controls a sequence of the modification of the PWM signal to selectively alter an output power spectrum of the modulated PWM signal.

Claims

1. A system comprising:

a first superframe structure including a first-superframe input configured to receive a first pulse width modulated (PWM) signal and including a first-superframe output, the first superframe structure configured to selectively apply a modulation operation to the first PWM signal according to a pre-determined superframe pattern to produce a superframed signal at the first-superframe output;

a second superframe structure including a second-superframe input configured to receive a second PWM signal that is a duty cycle complement of the first PWM signal and including a second-superframe output, the second superframe structure configured to selectively apply the modulation operation to the second PWM signal according to a complement of the pre-determined superframe pattern to produce a complementary-superframed signal at the second-superframe output;

a switch including a first input coupled to the first-superframe output, a second input coupled to the second-superframe output, a control input, and a switch output, the switch configured to receive a control signal at the control input and to selectively provide one of the superframed signal and the complementary-superframed signal to the switch output as a modulated output signal; and

wherein the modulation operation comprises one of a phase shift operation and a chop operation.

2. The system of claim 1, further comprising:

a gate driver including a driver input coupled to the switch output and including a driver output;

a first transistor including a first current electrode coupled to a power supply terminal, a second current electrode coupled to an output node, and a control electrode coupled to the driver output; and

a second transistor including a first current electrode coupled to the output node, a second current electrode coupled to a second power supply terminal, and a control electrode coupled to the driver output.

3. The system of claim 2, further comprising:

a low pass filter coupled to the output node; and

a speaker coupled to the low pass filter.

4. The system of claim 1, further comprising a control circuit configured to apply a superframe switching pattern to the control input to control the switch.

5. The system of claim 4, wherein the control circuit comprises:

a random number generator including an output for providing a random number;

a sign generator including an input coupled to the output of the random number generator and including an output for providing a binary output signal; and

a sample-hold circuit including a first input coupled to the output of the sign generator, a second input to receive a signal proportional to a carrier frequency of the first and second PWM signals, and an output coupled to the control input for providing the superframe switching pattern.

6. The system of claim 5, wherein:

the sample-hold circuit is configured to determine a sample-hold rate as a function of the carrier frequency divided by a superframe length of the pre-determined superframe pattern; and

the sample-hold circuit provides the superframe switching pattern to the control input according to the sample-hold rate.

7. The system of claim 6, where the carrier frequency divided by the superframe length is multiplied by a multiplier factor to determine the sample-hold rate.

8. The system of claim 7, wherein the multiplier factor is programmable to adjust the sample-hold rate to be a sub-multiple of the carrier frequency.

9. The system of claim 5, wherein the random number generator comprises a zero mean source with a white power spectrum.

10. The system of claim 5, wherein the random number generator comprises a zero mean source with a colored spectrum.

11. The system of claim 5, wherein the random number generator comprises a pseudo-random binary sequence generator.

12. A circuit comprising:

a plurality of superframe structures, each of the plurality of superframe structures including an input to receive a pulse width modulated (PWM) signal and including an output, each of the plurality of superframe structures configured to selectively apply a modulation operation to the PWM signal according to one of a plurality of superframe patterns to produce a superframed PWM signal;

a switch including a plurality of inputs coupled to the outputs of the plurality of superframe structures, a control input, and a switch output; and

a control circuit coupled to the control input and configured to control the switch to selectively provide the superframed PWM signal of one of the outputs of the plurality of superframe structures to the switch output as a modulated PWM signal.

13. The circuit of claim 12, wherein the plurality of superframe patterns have different pattern lengths.

14. The circuit of claim 12, wherein the plurality of superframe patterns have different sequences.

15. The circuit of claim 12, wherein the control circuit comprises:

a random number generator configured to produce random numbers with a white spectrum or a colored spectrum; and

a sample-hold module including an input coupled to the random number generator and an output coupled to the control input and configured to provide the random numbers to the switch at a sample-hold rate.

16. The circuit of claim 15, wherein the sample-hold rate is a function of a carrier frequency of the PWM signal divided by a length of a superframe applied to the superframed PWM signal.

17. A system comprising:

a pulse edge controller comprising;

a first input for receiving a pulse width modulated (PWM) signal;

a second input for receiving a duty cycle complement of the PWM signal;

a control input;

a first output;

a second output; and

logic circuitry coupled to the control input and configurable to selectively apply a modulation operation to the PWM signal and the duty cycle complement of the PWM signal to produce modulated PWM output signals at the first and second outputs in response to a superframe pattern received at the control input; and

a control circuit coupled to the control input and adapted to apply the superframe pattern selectively to the control input to control operation of the logic circuitry.

18. The system of claim 17, wherein the superframe pattern comprises a sequence of values defining if the modulation operation is applied.

19. The system of claim 18, wherein the control circuit controls the superframe pattern to repeat at a superframe rate or at a lower rate;

and

wherein a pattern length controls spacing between notches in a power spectrum of the modulated PWM output signals.

20. The system of claim 17, wherein the control circuit comprises a pattern generator configured to generate the superframe pattern for controlling the logic circuitry to selectively apply the modulation operation to produce the modulated PWM output signals according to the superframe pattern;

wherein the modulation operation comprises one of a phase shift operation and a chop operation.