Switched capacitor circuit and pipeline A/D converter
First Claim
1. A switched capacitor circuit comprising:
- an input terminal to which an analog input signal is inputted;
a plurality of sampling switches;
a plurality of sampling capacitors which are respectively connected to the plurality of sampling switches and which sample and hold the analog input signal by switching the plurality of sampling switches;
a plurality of operational amplifiers which are cascade-connected to each other and which amplify the analog input signal sampled and held by the plurality of sampling capacitors, so as to output the amplified analog input signal;
a Correlated Level Shift (CLS) circuit including a level shift capacitor which samples and level-shifts the analog input signal amplified with the plurality of operational amplifiers, and a plurality of level shift switches which switch connection states between the level shift capacitor and the plurality of operational amplifiers; and
an output terminal which outputs an output signal obtained by level-shifting of the amplified analog input signal,wherein the level shift capacitor is connected between an input of an operational amplifier arranged in a last stage of the plurality of operational amplifiers, and the output terminal, in a phase of sampling the amplified analog input signal.
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Accused Products
Abstract
There is provided a switched capacitor circuit and a pipeline A/D converter which are capable of suppressing electric power from being increased by utilizing a level-shift capacitor, even in a case where the switched capacitor circuit and the pipeline A/D converter are configured by utilizing a CLS technique. In the estimate phase, the capacitor Cc1 (level shift capacitor) is connected between the output terminal of the operational amplifier AMP2 and the inverting input terminal of the operational amplifier AMP2, so as to sample the output from the operational amplifier AMP2, and also to compensate the phase of the operational amplifier AMP2. Additionally, in the level shift phase, the capacitor Cc1 is connected between the output terminal of the operational amplifier 4 and the output terminal Vb, so as to be used to level-shift the output of the operational amplifier AMP2. Thereby, the load (the capacitance of the capacitors Cc1 and Cc2) on the operational amplifier AMP2 is reduced, thereby reducing the electric power of the switched capacitor circuit 200.
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Citations
7 Claims
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1. A switched capacitor circuit comprising:
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an input terminal to which an analog input signal is inputted; a plurality of sampling switches; a plurality of sampling capacitors which are respectively connected to the plurality of sampling switches and which sample and hold the analog input signal by switching the plurality of sampling switches; a plurality of operational amplifiers which are cascade-connected to each other and which amplify the analog input signal sampled and held by the plurality of sampling capacitors, so as to output the amplified analog input signal; a Correlated Level Shift (CLS) circuit including a level shift capacitor which samples and level-shifts the analog input signal amplified with the plurality of operational amplifiers, and a plurality of level shift switches which switch connection states between the level shift capacitor and the plurality of operational amplifiers; and an output terminal which outputs an output signal obtained by level-shifting of the amplified analog input signal, wherein the level shift capacitor is connected between an input of an operational amplifier arranged in a last stage of the plurality of operational amplifiers, and the output terminal, in a phase of sampling the amplified analog input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification