Solid state imaging device and method of driving the solid state imaging device

• US 7,924,335 B2
• Filed: 07/23/2008
• Issued: 04/12/2011
• Est. Priority Date: 07/26/2007
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Shimomura, Kenichi, Itakura, Keijirou
• Primary Examiner(s): Villecco; John M
• Application Number:
  US12/178,324
• Publication Number:
  US 20090027533A1
• Time in Patent Office: 993 Days
• Field of Search: 348/218.1, 348/229.1, 348/230.1, 348/308, 348/302, 348/297, 250/208.1, 341/155, 341/164, 341/165, 341/166
• US Class Current: 348/308
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A row scanner selects an arbitrary row in an pixel array unit. Per-column AD converters separately convert voltage signals respectively outputted from a column of a plurality of unit pixels in the selected arbitrary row into digital signals. A column scanner sequentially outputs the digital signals by a column-scanning operation thereof. An AD conversion result adjuster judges whether or not the digital signals reach a predetermined judgment value or the status equivalent to the digital signals reaching the predetermined judgment value is generated, and fixes the digital signals to digital pixel values set in accordance with the predetermined judgment value when a result of the judgment is positive.

Claims

1. A solid state imaging device comprising:

a pixel array unit where unit pixels each including a photoelectric conversion element are two-dimensionally arrayed in a matrix shape;

a row scanner for selecting an arbitrary row in the pixel array unit;

a plurality of column-by-column AD converters for separately converting voltage signals respectively outputted from the plurality of unit pixels in the selected arbitrary row into digital signals;

a column scanner for sequentially column-scanning the digital signals outputted by the plurality of column-by-column AD converters and outputting them;

a controller for timing-controlling the row scanner, the column-by-column AD converters and the column scanner; and

an AD conversion result adjuster for judging whether or not the digital signals reach a predetermined judgment value or the status equivalent to the digital signals reaching the predetermined judgment value is generated, and converting the digital signals into digital pixel values set in accordance with the predetermined judgment value when a result of the judgment is positive.

2. The solid state imaging device as claimed in claim 1, wherein

the controller sequentially executes a long-time exposure timing control and a short-time exposure timing control at an identical exposure time point, and

the column-by-column AD converters each output a combined digital signal in which the digital signal obtained in the long-time exposure timing control executed earlier and the digital signal obtained in the short-time exposure timing control executed later are combined at the identical exposure time point as the digital signal at the identical exposure time point.

3. The solid state imaging device as claimed in claim 1, wherein

the column-by-column AD converters each comprises:

a reference voltage generator for outputting a reference voltage changing over time;

a comparator for comparing each of the voltage signals outputted from a column of the plurality of unit pixels in the selected arbitrary row to the reference voltage; and

a counter for counting a clock from a time point when the reference voltage starts to change to a time point when the reference voltage reaches the voltage signal, and outputting a count value thereby obtained as the digital signal.

4. The solid state imaging device as claimed in claim 3, wherein

the counters are up-down counters capable of switching between down-counting and up-counting operations.

5. The solid state imaging device as claimed in claim 3, wherein

the AD conversion result adjuster judges whether or not the status is generated depending on whether or not the reference voltage reaches a reference voltage judgment value.

6. The solid state imaging device as claimed in claim 3, wherein

the reference voltage generator generates a signal in which a voltage is arithmetically changed over time as a reference voltage.

7. The solid state imaging device as claimed in claim 3, wherein

the AD conversion result adjuster judges whether or not the status is generated depending on whether or not the count value reaches a threshold value set in accordance with the predetermined judgment value.

8. The solid state imaging device as claimed in claim 1, wherein

the predetermined judgment value is set based on a maximum value of the voltage signal at which the voltage signal can maintain a linearity characteristic with respect to an amount of incident light from the photoelectric conversion elements.

9. The solid state imaging device as claimed in claim 1, wherein

the AD conversion result adjuster judges whether or not the status is generated depending on whether or not the reference voltage reaches a reference voltage judgment value, and changes the reference voltage to a value larger than a maximum amplitude of the voltage signal when a result of the judgment is positive.

10. The solid state imaging device as claimed in claim 1, further comprising a non-volatile memory capable of memorizing the predetermined judgment value and transferring the memorized predetermined judgment value to the AD conversion result adjuster.

11. The solid state imaging device as claimed in claim 10, wherein

the predetermined judgment value is set based on a maximum value of the voltage signal at which the voltage signal can maintain a linearity characteristic with respect to an amount of incident light from the photoelectric conversion elements, and

the non-volatile memory memorizes the predetermined judgment value measured when the solid state imaging device is manufactured.

12. The solid state imaging device as claimed in claim 1, wherein

the controller includes a first timing control mode for executing a single exposure timing control at an identical exposure time point and a second timing control mode for sequentially executing a long-time exposure timing control and a short-time exposure timing control at the identical exposure time point, and

the AD conversion result adjuster is operated in the second timing control mode.

13. The solid state imaging device as claimed in claim 12, wherein

the Ad conversion result adjuster is also operated in the first timing control mode.

14. The solid state imaging device as claimed in claim 13, wherein

the AD conversion result adjuster sets the reference voltage judgment values which are different to each other between in the first timing control mode and the second timing control mode.

15. The solid state imaging device as claimed in claim 12, wherein

the AD conversion result adjuster controls the reference voltage generator so that a rate of change over time of the reference voltage in the first timing control mode and a rate of change over time of the reference voltage in the second timing control mode are different to each other.

16. The solid state imaging device as claimed in claim 7, wherein

the AD conversion result adjuster sets a predetermined judgment value based on a maximum value of the voltage signal at which the voltage signal can maintain a linearity characteristic with respect to an amount of incident light from the photoelectric conversion elements, and

the AD conversion result adjuster sets a rate of change over change of the reference voltage over time by controlling the reference voltage generators so that the reference voltage can reach the threshold value within an operation time of the counters.

17. The solid state imaging device as claimed in claim 1, further comprising a line memory for temporarily memorizing the digital signals between the column-by-column AD converters and the column scanner.

18. The solid state imaging device as claimed in claim 1, wherein

the pixel array unit comprises a column signal wire, and a plurality of column-by-column analog CDSs are further provided between the column signal wire and the plurality of column-by-column AD converters.

21. The method of driving a solid state imaging device as claimed in claim 18, wherein

in the converting step, it is judged whether or not the status is generated depending on whether or not the reference voltage reaches a reference voltage judgment value, and the reference voltage is changed to a value larger than a maximum amplitude of the voltage signal when a result of the judgment is positive.

19. A method of driving a solid state imaging device including:

a selecting step for selecting unit pixels on a row-by-row basis in a pixel array unit where the unit pixels each including a photoelectric conversion element are two-dimensionally arrayed in a matrix shape;

a converting step for converting voltage signals outputted respectively from a column of the plurality of unit pixels in the row selected in the selecting step into digital signals; and

an outputting step for sequentially outputting the digital signals by a column-scanning operation thereof, wherein

in the converting step, it is judged whether or not the digital signals reach a predetermined judgment value or the status equivalent to the digital signals reaching the predetermined judgment value is generated, and the digital signals are fixed to digital pixel values set in accordance with the predetermined judgment value when a result of the judgment is positive.

20. The method of driving a solid state imaging device as claimed in claim 19, wherein

a long-time exposure timing control and a short-time exposure timing control are sequentially executed at an identical exposure time point in the selecting step, the converting step, and the output step, and

in the converting step, a combined digital signal in which the digital signal obtained in the long-time exposure timing control executed earlier at the identical exposure time point and the digital signal obtained in the short-time exposure timing control executed later are combined is used as the digital signal at the identical exposure time point.

22. The method of driving a solid state imaging device as claimed in claim 19, wherein

in the converting step, an counting operation is continued from a time point when a reference voltage changing over time starts to change to a time point when the reference voltage reaches the voltage signal, and a count value thereby obtained is outputted as the digital value.

23. The method of driving a solid state imaging device as claimed in claim 22, wherein

in the converting step, it is judged whether or not the status is generated depending on whether or not the count value reaches a threshold value set in accordance with the predetermined judgment value.