Stacked memory cell for use in high-density CMOS SRAM

• US 7,924,604 B2
• Filed: 10/27/2006
• Issued: 04/12/2011
• Est. Priority Date: 12/26/2005
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Uk-Rae, Yang, Hyang-Ja
• Primary Examiner(s): Le; Vu A
• Assistant Examiner(s): Yang; Han
• Application Number:
  US11/588,223
• Publication Number:
  US 20070147107A1
• Time in Patent Office: 1,628 Days
• Field of Search: 365/154, 365/174, 365/168
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A stacked memory cell for use in a high-density static random access memory is provided that includes first and second pull-down transistors formed in a first layer, a pass transistor connected between a gate of the second pull-down transistor and a bit line and formed in the first layer and a first and second pull-up transistors formed in a second layer located above the first layer and connected with the first and second pull-down transistors respectively to form an inverter latch. With the construction of a stacked memory cell having a lone pass transistor, cell size is reduced compared to a conventional six-transistor cell, and driving performance of the pass transistor can be improved.

Claims

1. A stacked single memory cell for use in a high-density static random access memory, the stacked memory cell comprising:

a first pull-down transistor and a second pull-down transistor both formed in an active layer located at a surface of a semiconductor substrate, the first and second pull-down transistors including respective first and second gates located on the active layer;

a first pull-up transistor and a second pull-up transistor both formed in a first channel layer located over and parallel to the active layer relative to the surface of the semiconductor substrate, the first and second pull-up transistors including respective third and fourth gates located on the first channel layer, wherein the first and second pull-up transistors are respectively connected to the first and second pull-down transistors to form an inverter latch; and

a pass transistor connected between a gate of the second pull-down transistor and a bit line, and formed in a second channel layer located over and parallel to the first channel layer such the first channel layer is interposed between the active layer and the second channel layer, wherein the pass transistor includes a fifth gate located on the second channel layer and connected to a word line,

wherein the pass transistor is a single pass transistor and the bit line is a single bit line.

2. The stacked memory cell according to claim 1, wherein at least one of the first and second channel layers is a silicon layer formed by selective epitaxial growth (SEG).

3. The stacked memory cell according to claim 1, wherein the first and second pull-down transistors are respective NMOS transistors.

4. The stacked memory cell according to claim 3, wherein the first and second pull-up transistors are respective PMOS transistors.

5. The stacked memory cell according to claim 4, wherein the pass transistor is an NMOS transistor.