Data storage in analog memory cells with protection against programming interruption

• US 7,924,613 B1
• Filed: 07/06/2009
• Issued: 04/12/2011
• Est. Priority Date: 08/05/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Sommer, Naftali, Shalvi, Ofir, Winter, Shai
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): TRAN, ANTHAN
• Application Number:
  US12/497,707
• Time in Patent Office: 645 Days
• Field of Search: 365/185.03
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A method for data storage includes storing first data in analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data. Second data is stored in the analog memory cells in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data. The first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell.

Claims

1. A method for data storage, comprising:

storing first data in analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data; and

storing in the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data,

wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell,

wherein the first and second programming operations are defined such that the analog values that are potentially reached during the second programming operation by the memory cells that store a first bit value of the first data are contained in a first range, and the analog values that are potentially reached during the second programming operation by the memory cells that store a second bit value of the first data, different from the first bit value, are contained in a second range that does not overlap the first range,

and comprising, following an interruption in the second programming operation, reconstructing the first data by reading the analog values from the memory cells using a read threshold positioned between the first and second ranges.

2. The method according to claim 1, wherein storing the first and second data comprises evaluating a condition with respect to the analog memory cells and, based on the condition, selecting to store the first and second data using one of a first version of the programming operations, in which at all times during the second programming operation the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell, and a second version of the programming operations that is different from the first version.

3. The method according to claim 2, wherein evaluating the condition comprises assessing whether the first and second data originate from different data items.

4. The method according to claim 2, wherein the analog memory cells are comprised in a memory device, wherein selection of the one of the first and second version is performed by circuitry that communicates with the memory device over an interface, and comprising reporting the selected version to the memory device via the interface.

5. The method according to claim 1, wherein the first programming operation represents a given bit value of the first data by analog values that are higher than the analog values representing the other bit value of the first data, and wherein storing the second data comprises applying the second programming operation to the memory cells holding the given bit value of the first data, and subsequently applying the second programming operation to the memory cells holding the other bit value of the first data.

6. A method for data storage, comprising:

storing first data in analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data; and

storing in the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data,

wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell,

wherein storing the first and second data comprises evaluating a condition with respect to the analog memory cells and, based on the condition, selecting to store the first and second data using one of a first version of the programming operations, in which at all times during the second programming operation the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell, and a second version of the programming operations that is different from the first version, and

wherein evaluating the condition comprises performing at least one action selected from a group of actions consisting of;

assessing a size of a data item to be stored in the analog memory cells;

identifying a pattern indicating an end of the data item to be stored in the analog memory cells; and

assessing an elapsed time since a previous programming operation.

7. A method for data storage, comprising:

storing first data in analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data; and

storing in the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data,

wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell,

wherein storing the first and second data comprises evaluating a condition with respect to the analog memory cells and, based on the condition, selecting to store the first and second data using one of a first version of the programming operations, in which at all times during the second programming operation the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell, and a second version of the programming operations that is different from the first version, and

wherein the condition is evaluated after the first data was stored using the second version and before storing the second data, and comprising, upon selecting the first version, adjusting the analog values of at least some of the analog memory cells to match the first version of the programming operations.

8. A data storage apparatus, comprising:

a plurality of analog memory cells; and

circuitry, which is configured to store first data in a group of the analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data, and to store in the group of the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data, wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell in the group remains unambiguously indicative of the respective bit value of the first data stored in that memory cell,

wherein the first and second programming operations are defined such that the analog values that are potentially reached during the second programming operation by the memory cells that store a first bit value of the first data are contained in a first range, and the analog values that are potentially reached during the second programming operation by the memory cells that store a second bit value of the first data, different from the first bit value, are contained in a second range that does not overlap the first range, and

wherein the circuitry is configured to reconstruct the first data following an interruption in the second programming operation by reading the analog values from the memory cells using a read threshold positioned between the first and second ranges.

9. The apparatus according to claim 8, wherein the circuitry is configured to evaluate a condition with respect to the analog memory cells and, based on the condition, to select to store the first and second data using one of a first version of the programming operations, in which at all times during the second programming operation the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell, and a second version of the programming operations that is different from the first version.

10. The apparatus according to claim 9, wherein the circuitry is configured to evaluate the condition by assessing whether the first and second data originate from different data items.

11. The apparatus according to claim 8, wherein the analog memory cells are comprised in a memory device, wherein the circuitry is separate from the memory device and communicates with the memory device over an interface, and wherein the circuitry is configured to report the selected version to the memory device via the interface.

12. The apparatus according to claim 8, wherein the first programming operation represents a given bit value of the first data by analog values that are higher than the analog values representing the other bit value of the first data, and wherein the circuitry is configured to store the second data by applying the second programming operation to the memory cells holding the given bit value of the first data, and subsequently applying the second programming operation to the memory cells holding the other bit value of the first data.

13. A data storage apparatus, comprising:

a plurality of analog memory cells; and

circuitry, which is configured to store first data in a group of the analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data, and to store in the group of the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data, wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell in the group remains unambiguously indicative of the respective bit value of the first data stored in that memory cell,

wherein the circuitry is configured to evaluate a condition with respect to the analog memory cells and, based on the condition, to select to store the first and second data using one of a first version of the programming operations, in which at all times during the second programming operation the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell, and a second version of the programming operations that is different from the first version, and

wherein the circuitry is configured to evaluate the condition by performing at least one action selected from a group of actions consisting of;

assessing a size of a data item to be stored in the analog memory cells;

identifying a pattern indicating an end of the data item to be stored in the analog memory cells; and

assessing an elapsed time since a previous programming operation.

14. A data storage apparatus, comprising:

a plurality of analog memory cells; and

circuitry, which is configured to store first data in a group of the analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data, and to store in the group of the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data, wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell in the group remains unambiguously indicative of the respective bit value of the first data stored in that memory cell,

wherein the circuitry is configured to evaluate a condition with respect to the analog memory cells and, based on the condition, to select to store the first and second data using one of a first version of the programming operations, in which at all times during the second programming operation the analog value of each memory cell remains unambiguously indicative of the respective bit value of the first data stored in that memory cell, and a second version of the programming operations that is different from the first version, and

wherein the circuitry is configured to evaluate the condition after storing the first data using the second version and before storing the second data, and, upon selecting the first version, to adjust the analog values of at least some of the analog memory cells to match the first version of the programming operations.

15. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory device comprising a plurality of analog memory cells; and

circuitry, which is configured to store first data in a group of the analog memory cells using a first programming operation, which writes to the memory cells respective analog values representing respective bit values of the first data, and to store in the group of the analog memory cells second data in addition to the first data using a second programming operation, which modifies the respective analog values of the memory cells so as to represent bit value combinations of the first and second data, wherein the first and second programming operations are defined such that, at all times during the second programming operation, the analog value of each memory cell in the group remains unambiguously indicative of the respective bit value of the first data stored in that memory cell,

wherein the first and second programming operations are defined such that the analog values that are potentially reached during the second programming operation by the memory cells that store a first bit value of the first data are contained in a first range, and the analog values that are potentially reached during the second programming operation by the memory cells that store a second bit value of the first data, different from the first bit value, are contained in a second range that does not overlap the first range, and

wherein the circuitry is configured to reconstruct the first data following an interruption in the second programming operation by reading the analog values from the memory cells using a read threshold positioned between the first and second ranges.