Operation of a non-volatile memory array
First Claim
Patent Images
1. A non-volatile memory (“
- NVM”
) device comprising a first buffer adapted to receive data from an interface;
a second buffer adapted to receive data derived from data in said first buffer; and
control logic adapted to program an NVM array using data in said second buffer, wherein programming of the NVM array includes modifying data in said second buffer during a first phase of programming and refreshing data in said second buffer with at least some data from said first buffer prior to a second phase of programming.
6 Assignments
0 Petitions
Accused Products
Abstract
A cache programming operation which requires 2 SRAMs (one for the user and one for the array) may be combined with a multi-level cell (MLC) programming operation which also requires 2 SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs (or buffers). One of the buffers (User SRAM) receives and stores user data. The other of the two buffers (Cache SRAM) may perform a caching function as well as a verify function. In this manner, if a program operation fails, the user can have its original data back so that he can try to reprogram it to a different place (address).
-
Citations
17 Claims
-
1. A non-volatile memory (“
- NVM”
) device comprising a first buffer adapted to receive data from an interface;a second buffer adapted to receive data derived from data in said first buffer; and control logic adapted to program an NVM array using data in said second buffer, wherein programming of the NVM array includes modifying data in said second buffer during a first phase of programming and refreshing data in said second buffer with at least some data from said first buffer prior to a second phase of programming. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- NVM”
-
12. A method of programming a non-volatile memory (“
- NVM”
) device comprising;placing data in a first buffer; placing data in a second buffer derived from data in the first buffer; and programming an NVM array using data in said second buffer, wherein programming of the NVM array includes modifying data in said second buffer during a first phase of programming and refreshing data in said second buffer with at least some data from said first buffer prior to a second phase of programming. - View Dependent Claims (13, 14, 15, 16, 17)
- NVM”
Specification