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Three-dimensional memory device and programming method

  • US 7,924,629 B2
  • Filed: 12/24/2008
  • Issued: 04/12/2011
  • Est. Priority Date: 12/28/2007
  • Status: Active Grant
First Claim
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1. A method of performing a programming operation within a three-dimensional memory device, the three-dimensional memory device comprising a stacked plurality of layers, each layer comprising a memory array, and each memory array comprising a string of memory cells, the method comprising:

  • for each unselected string associated with an unselected layer in the plurality of layers, charging a channel of memory cells associated with the unselected strings with a shut-off voltage; and

    thereafter,programming a selected string associated with a selected layer of the plurality of layers,wherein the channels of the memory cells of the unselected strings are charged by ground selection transistors, and the shut-off voltage is equal to a voltage greater than or equal to a power supply voltage less a threshold voltage of the ground selection transistors disposed in the unselected layers, andrespective strings associated with each one of the plurality of layers are commonly connected to a shared bit line.

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