Three-dimensional memory device and programming method
First Claim
1. A method of performing a programming operation within a three-dimensional memory device, the three-dimensional memory device comprising a stacked plurality of layers, each layer comprising a memory array, and each memory array comprising a string of memory cells, the method comprising:
- for each unselected string associated with an unselected layer in the plurality of layers, charging a channel of memory cells associated with the unselected strings with a shut-off voltage; and
thereafter,programming a selected string associated with a selected layer of the plurality of layers,wherein the channels of the memory cells of the unselected strings are charged by ground selection transistors, and the shut-off voltage is equal to a voltage greater than or equal to a power supply voltage less a threshold voltage of the ground selection transistors disposed in the unselected layers, andrespective strings associated with each one of the plurality of layers are commonly connected to a shared bit line.
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Abstract
A programming method and a three-dimensional memory device are disclosed. The three-dimensional memory device includes a stacked plurality of layers, each layer having a memory array, and each memory array having a string of memory cells. The programming method includes, for each unselected string associated with an unselected layer in the plurality of layers, charging the channel of memory cells associated with unselected string with a shut-off voltage, and thereafter programming a selected string associated with a selected layer in the plurality of layers.
45 Citations
15 Claims
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1. A method of performing a programming operation within a three-dimensional memory device, the three-dimensional memory device comprising a stacked plurality of layers, each layer comprising a memory array, and each memory array comprising a string of memory cells, the method comprising:
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for each unselected string associated with an unselected layer in the plurality of layers, charging a channel of memory cells associated with the unselected strings with a shut-off voltage; and
thereafter,programming a selected string associated with a selected layer of the plurality of layers, wherein the channels of the memory cells of the unselected strings are charged by ground selection transistors, and the shut-off voltage is equal to a voltage greater than or equal to a power supply voltage less a threshold voltage of the ground selection transistors disposed in the unselected layers, and respective strings associated with each one of the plurality of layers are commonly connected to a shared bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of performing a programming operation within a three-dimensional memory device, the three-dimensional memory device comprising a stacked plurality of layers, each layer comprising a memory array, and each memory array comprising a string of memory cells, the method comprising:
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for each unselected string associated with an unselected layer in the plurality of layers, charging a channel of memory cells associated with the unselected strings with a shut-off voltage; and
thereafter,programming a selected string associated with a selected layer of the plurality of layers, wherein respective strings associated with each one of the plurality of layers are respectively connected to one of a plurality of layer specific common source lines, and wherein the programming operation comprises applying a power supply voltage to a selected common source line in the plurality of common source lines associated with the selected layer, and applying an elevated voltage higher than the power supply voltage to unselected common source lines in the plurality of common source lines associated with the unselected layers. - View Dependent Claims (9, 10, 11, 12)
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13. A memory system including a memory controller and a three-dimensional memory device, wherein the three-dimensional memory device comprises:
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a stacked plurality of layers, each layer comprising a memory array having a string of memory cells, wherein programming data to a memory cell of a respective string is controlled by a selection transistor and a ground selection transistor associated with the string; a plurality of shared word lines configured to program data to memory cells in strings associated with each one of the plurality of layers; and a shared bit line configured to program data to memory cells in strings associated with each one of the plurality of layers, wherein the memory controller is configured to receive an address defining a selected layer from the plurality of layers containing a memory cell to be programmed and unselected layers, thereafter charge a channel of memory cells in strings associated with the unselected layers with a shut-off voltage, and thereafter program a memory cell of a string associated with the selected layer, and wherein the channels of the memory cells in strings associated with the unselected layers are charged by the ground selection transistors under control of the memory controller, and the shut-off voltage is equal to a voltage greater than or equal to a power supply voltage less a threshold voltage of the ground selection transistors disposed in the unselected layers, and respective strings associated with each one of the plurality of layers are commonly connected to a shared bit line. - View Dependent Claims (14, 15)
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Specification