Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution

• US 7,925,861 B2
• Filed: 01/31/2007
• Issued: 04/12/2011
• Est. Priority Date: 04/09/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: McConnell, Ray, Rhoades, John, Faulds, Gordon, David, Russell, Greer, Trey, Atkin, Phil, Stuttard, Dave, Day, Tim, Williams, Dave, O'Dea, Eamon, Cameron, Ken, Winser, Paul
• Primary Examiner(s): Kim; Kenneth S
• Application Number:
  US11/669,868
• Publication Number:
  US 20070226458A1
• Time in Patent Office: 1,532 Days
• Field of Search: None
• US Class Current: 712/22
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A data processor comprises a plurality of processing elements arranged in a first plurality of single instruction multiple data (SIMD) processing arrays, and comprises a second plurality of controllers for transferring instructions to the processing arrays. Each controller is operable to retrieve a plurality of incoming instruction streams in parallel with one another and operable to supply incoming instruction streams to one of a plurality of processing arrays.

Claims

1. A multithreaded data processor operable to process a plurality of threads, the data processor comprising:

a plurality of single instruction multiple data (SIMD) processing arrays, each processing array comprising a plurality of processing elements (PEs), each PE operable to receive a selected one of the plurality of threads;

a thread manager operable to transfer the threads to an array controller, the thread manager comprising;

a fetch unit operable to retrieve the threads in parallel with one another;

a thread scheduler operable to schedule processing priority for each thread from among the plurality of threads;

wherein the fetch unit is further operable to transfer sequentially a plurality of core instructions from each selected thread from among the plurality of threads to the array controller; and

wherein;

the array controller is operable to transfer each selected thread from among the plurality of threads to the plurality of SIMD processing arrays on the basis of a priority status allocated to the threads.

2. A data processor as claimed in claim 1, wherein the array controller is operable to transfer each of the threads to a single SIMD processing array.

3. A data processor as claimed in claim 1, wherein the array controller is operable to transfer each of the threads to at least two of the plurality of SIMD processing arrays.

4. A data processor as claimed in claim 1, wherein each thread manager comprises a cache memory for storing retrieved threads.

5. A data processor as claimed in claim 1, wherein each thread manager comprises a first-in-first-out buffer for storing retrieved threads.

6. A data processor as claimed in claim 1, wherein each thread manager comprises a synchronization controller for controlling synchronization between threads.

7. A data processor as claimed in claim 1, wherein each thread manager comprises a synchronization controller for controlling synchronization between threads and external hardware units.

8. A data processor as claimed in claim 1, wherein each thread manager comprises:

a thread processor for controlling a plurality of threads;

a synchronization controller for controlling synchronization between threads;

a status block for providing status information regarding each of the threads; and

a scheduling means connected to receive status information, and operable to determine which of the threads is to be active.

9. A data processor as claimed in claim 1, wherein each thread manager is operable to assign threads respective relative priority levels.

10. A data processor as claimed in claim 1, wherein each thread manager comprises a scheduler connected to receive status information from functional units external to the array of processing elements, and operable to schedule threads using such received status information.

25. A data processor as claimed in claim 1, wherein the array controller comprises an instruction launcher operable to receive the plurality of threads from the thread manager.

26. A data processor as claimed in claim 25, wherein the array controller comprises an instruction sequencer;

and a load/store controller and wherein the instruction launcher is operable to direct instruction information to either the instruction sequencer or a load/store controller, the instruction sequencer operable to receive instruction information relating to data processing of the plurality of processing elements of the SIMD processing arrays, the load/store controller operable to receive instruction information relating to data transfer operations.

27. A data processor as claimed in claim 1, wherein the array controller comprises a scoreboard unit, the scoreboard unit operable to store information regarding the use of processing elements registers by each thread.

28. A data processor as claimed in claim 1 further comprising a channel controller operable to asynchronously control computation and external input/output operations and wherein the thread manager is operable to synchronize the operations of the processing elements of the SIMD arrays with the input/output operations.

11. A method for controlling a data processor operable to process a plurality of threads, the data processor including:

a plurality of single instruction multiple data (SIMD) processing arrays, each processing array comprising a plurality of processing elements (PEs), each PE operable to receive a selected one of the plurality of threads;

a thread manager operable to transfer the threads to an array controller, the thread manager comprising a fetch unit operable to retrieve the threads in parallel with one another;

a thread scheduler operable to schedule processing priority for each thread from among the plurality of threads;

wherein fetch unit is further operable to transfer sequentially a plurality of core instructions from each selected thread from among the plurality of threads to the array controller; and

wherein

the array controller is operable for transferring each instruction stream from among the plurality of threads to the plurality of SIMD processing arrays on the basis of a priority status allocated to the threads, the method comprising;

retrieving by the fetch unit a plurality of incoming threads in parallel with one another; and

transferring sequentially a plurality of instructions from a selected one of the retrieved threads to the array controller for transfer to the plurality of SIMD processing arrays on the basis of a priority status allocated to the threads.

12. A method as claimed in claim 11, wherein the array controller transfers each of the threads to a single SIMD processing array.

13. A method as claimed in claim 11, wherein the array controller transfers each of the threads to at least two of the plurality of SIMD processing arrays.

14. A method as claimed in claim 11, wherein transferring the retrieved instruction streams includes transferring the retrieved threads to one or more function controllers operable to control respective functional units.

15. A method as claimed in claim 11, wherein transferring the retrieved threads includes transferring the retrieved threads to one or more function controllers operable to control the processing elements in a corresponding processor array.

16. A method as claimed in claim 11, wherein transferring the retrieved threads includes transferring the retrieved threads to one or more function controllers operable to control input/output functions of respective arrays of processing elements.

17. A method as claimed in claim 11, wherein transferring the retrieved threads includes transferring the retrieved threads to a plurality of first function controllers operable to control the processing elements in respective processor arrays, and to a plurality of second function controllers operable to control input/output functions of respective arrays of processing elements, the first and second function controllers operating asynchronously.

18. A method as claimed in claim 11, wherein transferring the retrieved threads includes transferring selectively the retrieved threads to either an array controller which controls data processing of the processor arrays, or to a channel controller which controls the transfer of data to and from the processing elements in the processor arrays.

19. A method as claimed in claim 11, comprising storing the retrieved threads in a cache memory.

20. A method as claimed in claim 11, comprising storing the retrieved threads in a first-in-first-out buffer.

21. A method as claimed in claim 11, comprising controlling synchronization between threads.

22. A method as claimed in claim 11, comprising controlling synchronization between threads and external hardware units.

23. A method as claimed in claim 11, comprising controlling a plurality of threads;

a synchronization controller for controlling synchronization between threads;

a status block for providing status information regarding each of the threads; and

a scheduling means connected to receive status information, and operable to determine which of the threads is to be active.

24. A method as claimed in claim 11, comprising assigning threads respective relative priority levels.