Using non-lossless compression to save power

• US 7,925,907 B1
• Filed: 12/12/2005
• Issued: 04/12/2011
• Est. Priority Date: 12/12/2005
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Reed, David G.
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): Yanchus, III; Paul B
• Application Number:
  US11/301,850
• Time in Patent Office: 1,947 Days
• Field of Search: 713300-375
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Circuits, methods, and systems that reduce or eliminate the number of data transfers between a system memory and a graphics processor under certain conditions. After inactivity by a user of an electronic device is detected, the color fidelity of pixels being displayed is reduced. Color fidelity can be reduced by compressing pixel values, and the compression may be non-lossless, for example, pixel data bits may be truncated. The degree of compression can be progressively increased for longer durations of inactivity, and this progression may be limited by a threshold. Inactivity may be detected by a lack of input from devices such as a keyboard, pen, mouse, or other input device. Once activity is resumed, uncompressed pixel data, or pixel data that is compressed in a lossless manner, is displayed.

Claims

1. A method of reducing power dissipation comprising:

monitoring user activity;

if a first duration passes without user activity occurring, then

reducing a color fidelity of a plurality of pixels;

storing the plurality of pixels having a reduced color fidelity in a first memory;

storing the plurality of pixels having a reduced color fidelity in a second memory; and

until user activity is detected;

reading the plurality of pixels having the reduced fidelity from the second memory without reading the plurality of pixels having the reduced fidelity from the first memory; and

displaying the plurality of pixels having the reduced color fidelity;

otherwise,

not reducing the color fidelity of the plurality of pixels; and

displaying the plurality of pixels.

2. The method of claim 1 wherein the color fidelity of the plurality of pixels is reduced using a non-lossless compression algorithm.

3. The method of claim 1 wherein the color fidelity of the plurality of pixels is reduced by truncating a value of each of the plurality of pixels.

4. The method of claim 1 further comprising:

if a second duration passes without user activity, the second duration longer than the first duration, then

further reducing the color fidelity of the plurality of pixels; and

displaying the plurality of pixels having the further reduced color fidelity.

5. The method of claim 1 further comprising:

if a second duration passes without user activity, the second duration longer than the first duration;

then

reducing a power supply for a central processing unit.

6. The method of claim 1 wherein reducing a color fidelity of a plurality of pixels comprises reducing a color fidelity of each pixel to be displayed.

7. An integrated circuit comprising:

a graphics processing unit comprising;

a first circuit configured to detect user activity;

a second circuit configured to compress pixel data;

a third circuit configured to write compressed pixel data to an external memory and to read compressed pixel data from the external memory; and

an internal memory configured to store the compressed pixel data;

wherein when the first circuit detects user inactivity for a first duration, the second circuit compresses pixel data using a first algorithm, the third circuit writes the compressed pixel data to the external memory, then the third circuit reads the compressed pixel data from the external memory and the compressed pixel data is stored in the internal memory, and

wherein compressed pixel data stored in the internal memory is read multiple times.

8. The integrated circuit of claim 7 wherein the first algorithm is non-lossless.

9. The integrated circuit of claim 7 wherein when the first circuit detects user inactivity for a second duration, the second circuit compresses pixel data using a second algorithm.

10. The integrated circuit of claim 7 wherein the first algorithm is to truncate pixel data bits.

11. The integrated circuit of claim 7 wherein when the first circuit detects user activity within the first duration, the second circuit does not compress pixel data using the first algorithm.

12. The integrated circuit of claim 7 wherein the integrated circuit is an Integrated Graphics Processor.

13. The integrated circuit of claim 7 wherein when the first circuit detects user inactivity for a first duration, the second circuit compresses pixel data using a first algorithm for every pixel to be displayed.

14. A method of reducing power dissipation by compressing pixel data comprising:

detecting a user'"'"'s inactivity;

receiving a first plurality of pixel values from a first memory;

compressing the pixel values;

storing the compressed pixel values in the first memory;

receiving the compressed pixel values from the first memory;

storing the compressed pixel values in a second memory; and

displaying the compressed pixel values more than once until user activity is detected.

15. The method of claim 14 wherein the compressed pixel values comprise a plurality of lines of an image frame.

16. The method of claim 14 wherein the compressed pixel values comprise an image frame.

17. The method of claim 16 further comprising:

reducing a power supply for a central processing unit.

18. The method of claim 14 wherein the pixel values are compressed by truncating bits of the pixel values.

19. The method of claim 14 wherein the inactivity is detected by monitoring activity on one or more input devices.

20. The method of claim 14 wherein the first memory is a system memory and the second memory is located on a graphics processing unit.

21. The method of claim 20 wherein the graphics processing unit is located on an integrated graphics processor.

22. The method of claim 14 further comprising:

detecting activity by the user;

receiving a second plurality of pixel values from the first memory; and

displaying the second plurality of pixel values.

23. The method of claim 14 further wherein the first plurality of pixels comprises each pixel to be displayed.

24. The method of claim 14 further comprising:

receiving the compressed pixel values from the second memory; and

re-displaying the compressed pixel values.