Information processing apparatus for performing a system boot by using programs stored in a non-volatile storage device

• US 7,925,928 B2
• Filed: 11/13/2007
• Issued: 04/12/2011
• Est. Priority Date: 12/25/2003
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Sumida, Keizo, Mino, Yoshiteru, Yamamoto, Yasunori
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): BUTLER, SARAI E
• Application Number:
  US11/984,008
• Publication Number:
  US 20080082860A1
• Time in Patent Office: 1,246 Days
• Field of Search: 714/8, 714/42, 714/36, 713/2
• US Class Current: 714/36
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1417 Boot up procedures

Abstract

After power activation, a transferer 14 detects a bootstrap program 111 having a first error check code 114 assigned thereto and being stored in a first storage device 11, subjects the bootstrap program 111 to an error detection/correction process, and transfers the bootstrap program 111 to the second storage device 12. If the transfer is properly completed, by executing the bootstrap program 111 on the second storage device 12, the CPU 10 performs an error detection/correction process for a main program 112 having a second error check code 115 assigned thereto, and transfers the main program 112 to a third storage device 13, after which the CPU'"'"'s control branches out to the main program 112 on the third storage device 13. As a result, system boot can be performed without employing a NOR type flash memory.

Claims

1. An information processing apparatus for performing a system boot by using programs stored in a non-volatile storage device, the apparatus comprising:

a CPU;

a non-volatile first storage device for storing, as programs to be executed by the CPU, a bootstrap program having a first check code assigned thereto and a main program having a second check code calculated by a method different from that used for calculating the first check code;

a volatile second storage device for storing the program read from the first storage device; and

a transferer for reading a program stored in the first storage device,

wherein during system boot, the transferer reads the bootstrap program from the first storage device, subjects the bootstrap program to an error detection/correction process based on the first check code, and transfers the processed bootstrap program to the second storage device.

2. The information processing apparatus according to claim 1, wherein the CPU transfers the main program stored in the first storage device to the second storage device in accordance with the bootstrap program stored in the second storage device, and subjects the main program to an error detection/correction process based on the second check code.

3. The information processing apparatus according to claim 1, wherein the transferer includes:

a transfer control section for controlling the transfer of the bootstrap program; and

an error processing section for performing the error detection/correction process.

4. The information processing apparatus according to claim 1, wherein:

the first storage device includes a plurality of blocks each of which is identified as either a normal block or a bad block, and

the bootstrap program, the main program and stored position information representing a stored position of the main program in the first storage device are stored in a normal block of the first storage device.

5. The information processing apparatus according to claim 4, wherein:

the bootstrap program includes the stored position information and an error processing program for performing the error detection/correction process based on the second check code, and

the CPU transfers the main program stored in the first storage device to the second storage device via the transferer in accordance with the stored position information after the error detection/correction process based on the first check code, and performs an error detection/correction process for the main program stored in the second storage device in accordance with the error processing program after the error detection/correction process based on the first check code.

6. The information processing apparatus according to claim 4, wherein:

the first storage device stores the stored position information having the first check code assigned thereto,

the transferer performs an error detection/correction process based on the first check code also for the stored position information read from the first storage device,

the boot strap program includes an address at which the stored position information is stored in the first storage device and error processing program for performing the error detection/correction process based on the second check code, and

the CPU transfers the stored position information stored in the first storage device to the second storage device via the transferer by using the address after the error detection/correction process based on the first check code, transfers the main program stored in the first storage device to the second storage device via the transferer in accordance with the stored position information after the error detection/correction process based on the first check code, and performs an error detection/correction process for the main program stored in the second storage device in accordance with the error processing program after the error detection/correction process based on the first check code.

7. The information processing apparatus according to claim 4, wherein:

the bootstrap program is stored in the normal block of the first storage device in data units of a predetermined, and

the transferer reads each data unit of the predetermined size of the bootstrap program from the first storage device, subjects the data unit to an error detection/correction process based on the first check code, and transfers the processed data unit to the second storage device.

8. The information processing apparatus according to claim 7, wherein:

if an uncorrectable error is detected as a result of performing the error detection/correction process based on the first check code for the data unit of the predetermined size read from the first storage device, the transferer reads a next data unit to be processed from a normal block next to the block containing the data unit.

9. The information processing apparatus according to claim 7, wherein:

the bootstrap program is stored in the normal block of the first storage device in data units of the predetermined size and with a collation code assigned to each data unit, and

the transferer retains reference data for the collation code, and if a collation code which is identical to the reference data is assigned to the data unit of the predetermined size read from the first storage device, transfers the read data unit to the second storage device.

10. The information processing apparatus according to claim 9, wherein

the transferer is arranged so as to allow the reference data to be changed based on given data.

11. The information processing apparatus according to claim 1, wherein the transferer includes:

a transfer control section for controlling the transfer of the bootstrap program;

a first error processing section for performing the error detection/correction process based on the first check code for the bootstrap program being transferred; and

a second error processing section for performing at least a portion of the error detection/correction process based on the second check code for the main program read from the first storage device.

12. The information processing apparatus according to claim 11, wherein:

the second error processing section calculates a syndrome based on the second check code with respect to the main program read from the first storage device, and

in accordance with the boot strap program stored in the second storage device, the CPU performs rest of the error detection/correction process based on the second check code for the main program read from the first storage device by using the syndrome calculated by the second error processing section.

13. The information processing apparatus according to claim 11, wherein

the transferer switches the processing section to process the program read from the first storage device from the first error processing section to the second error processing section under control of CPU.

14. The information processing apparatus according to claim 11, wherein:

if the second error processing section has detected an uncorrectable error, the transferer notifies the CPU of a failure of the transfer, and

the CPU performs an abnormality handling process when receiving a notification of a failure of the transfer.

15. The information processing apparatus according to claim 1, wherein

in addition to transferring the bootstrap program, under control of the CPU, the transferer reads the main program from the first storage device in data units of a predetermined size, and transfers each data unit read to the second storage device.

16. A ROM image generation apparatus for preparing the first storage device which is employed for the information processing apparatus according to anyone of claims 1 to 15.

17. The ROM image generation apparatus according to claim 16, comprising:

a bad block information retaining section for retaining position information of the bad block included in the storage device to which the ROM image is to be written;

a code information management section for managing types of check code in association with types of input data;

an image reformatting section for converting input data to a format suitable for assigning thereto a check code associate with the type of input data; and

a write image generation section for, by referring to the position information stored in the bad block information retaining section, merging a plurality of data having been reformatted by the image reformatting section into a single data while avoiding the bad block, and assigning the check code associated with the type of input data to the merged data.

18. The ROM image generation apparatus according to claim 17, further comprising a collation code retaining section for retaining a collation code,

wherein the image reformatting section assigns to the input data the collation code retained in the collation code retaining section.

19. The ROM image generation apparatus according to claim 18, further comprising a memory control section for performing a process of searching for a position of the bad block in the storage device to obtain the position information of the bad block and a process of writing the data generated by the write image generation section to the storage device.