Sets of rate-compatible universal turbo codes nearly optimized over various rates and interleaver sizes

• US 7,925,963 B2
• Filed: 05/04/2009
• Issued: 04/12/2011
• Est. Priority Date: 01/23/1998
• Status: Expired due to Fees

• Current Assignee: DTVG Licensing, Inc. (AT&T, Inc.)
• Original Assignee: DTVG Licensing, Inc. (AT&T, Inc.)
• Inventors: Hammons, A. Roger Jr., Eroz, Mustafa
• Primary Examiner(s): Baker; Stephen M
• Application Number:
  US12/435,237
• Publication Number:
  US 20090217141A1
• Time in Patent Office: 708 Days
• Field of Search: 714/790
• US Class Current: 714/790
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/6312 Error control coding in combination with data compression
• CPC Class Codes: H03M 13/6381 Rate compatible punctured turbo [RCPT] codes
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 1/0069 Puncturing patterns

Abstract

A method and apparatus for Turbo encoding uses a set of rate-compatible Turbo Codes optimized at high code rates and derived from a universal constituent code. The Turbo Codes have rate-compatible puncturing patterns.

The method comprises: encoding a signal at a first and second encoder using a best rate 1/2 constituent code universal with higher code rates, the first encoder and the second encoder each producing a respective plurality of parity bits for each information bit; puncturing the respective plurality of parity bits at each encoder with a higher rate best puncturing patterns; and puncturing the respective plurality of parity bits at each encoder with a lower rate best puncturing pattern. In a variation, the best rate 1/2 constituent code represents a concatenation of polynomials 1+D²+D³ (octal 13) and 1+D+D³ (octal 15), D a data bit. A Turbo Encoder is provided which has hardware to implement the method.

Claims

1. A method comprising:

generating a first set of parity bits based on information bits and a second set of parity bits based on interleaved information bits,

wherein the first set of parity bits and the second set of parity bits correspond to respective constituent codes that are universally adapted to accommodate a variety of interleaver depths and code rates,

wherein the sets of parity bits are punctured according to one of the code rates to output a coded signal.

2. A method according to claim 1, wherein the constituent codes exhibit a rate of 1/2 and have a transfer function of G(D)=[1, (1+D+D³)/(1+D²+D³)], D denoting unit delay in presentation of the information bits for generation of the parity bits.

3. A method as claimed in claim 1, wherein the constituent codes exhibit a rate of 1/3 and have a transfer function of G(D)=[1, (1+D+D³)/(1+D²+D³), (1+D+D²+D³)/(1+D²+D³)], D denoting unit delay in presentation of the information bits for generation of the parity bits.

4. A method according to claim 1, further comprising:

selecting a candidate system rate for the constituent codes;

evaluating performance of the code rates formed by the constituent codes according to a first interleaver depth and a plurality of test patterns;

determining a subgroup of candidate pairs of constituent codes, wherein other interleaver depths are applied to the subgroup; and

determining the universal constituent codes from the subgroup yielding best performance for the interleaver depths.

5. A method according to claim 1, wherein the coded signal is a Turbo coded signal with a code rate of either 1/2, 1/3, or 1/4.

6. A method according to claim 1, wherein the first set of parity bits is generated at a first encoder, and the second set of parity bits is generated at a second encoder.

7. A method according to claim 1, further comprising:

modulating the coded signal according to a modulation scheme that includes either a Code Division Multiple Access (CDMA) or Time Division Multiple Access (TDMA).

8. A transmitter comprising:

an encoding circuit configured to generate a first set of parity bits based on information bits and a second set of parity bits based on interleaved information bits,

wherein the first set of parity bits and the second set of parity bits correspond to respective constituent codes that are universally adapted to accommodate a variety of interleaver depths and code rates,

wherein the sets of parity bits are punctured according to one of the code rates to output a coded signal.

9. A transmitter according to claim 8, wherein the constituent codes exhibit a rate of 1/2 and have a transfer function of G(D)=[1, (1+D+D³)/(1+D²+D³)], D denoting unit delay in presentation of the information bits for generation of the parity bits.

10. A transmitter as claimed in claim 8, wherein the constituent codes exhibit a rate of 1/3 and have a transfer function of G(D)=[1, (1+D+D³)/(1+D²+D³), (1+D+D²+D³)/(1+D²+D³)], D denoting unit delay in presentation of the information bits for generation of the parity bits.

11. A transmitter according to claim 8, wherein the coded signal is a Turbo coded signal with a code rate of either 1/2, 1/3, or 1/4.

12. A transmitter according to claim 8, wherein the first set of parity bits is generated at a first encoder, and the second set of parity bits is generated at a second encoder.

13. A transmitter according to claim 8, further comprising:

a modulator configured to modulate the coded signal according to a modulation scheme that includes either a Code Division Multiple Access (CDMA) or Time Division Multiple Access (TDMA).

14. An apparatus comprising:

a first encoder configured to received information bits and to generate a first set of parity bits;

a second encoder configured to generated a second set of parity bits; and

an interleaver coupled to the first encoder and the second encoder, the interleaver being configured to randomize order of the information bits to the second encoder,

wherein the first set of parity bits and the second set of parity bits correspond to respective constituent codes that are universally adapted to accommodate a variety of interleaver depths and code rates.

15. An apparatus according to claim 14, wherein the constituent codes exhibit a rate of 1/2 and have a transfer function of G(D)=[1, (1+D+D³)/(1+D²+D³)], D denoting unit delay in presentation of the information bits for generation of the parity bits.

16. An apparatus as claimed in claim 14, wherein the constituent codes exhibit a rate of 1/3 and have a transfer function of G(D)=[1, (1+D+D³)/(1+D²+D³), (1+D+D²+D³)/(1+D²+D³)], D denoting unit delay in presentation of the information bits for generation of the parity bits.

17. An apparatus according to claim 14, wherein the coded signal is a Turbo coded signal with a code rate of either 1/2, 1/3, or 1/4.

18. An apparatus according to claim 14, wherein the sets of parity bits are punctured according to one of the code rates to output a coded signal, the coded signal being modulated according to a modulation scheme that includes either a Code Division Multiple Access (CDMA) or Time Division Multiple Access (TDMA).