Semiconductor package and method therefor

• US 7,927,927 B2
• Filed: 08/13/2001
• Issued: 04/19/2011
• Est. Priority Date: 09/04/1996
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Nelson, Keith E., Quan, Son Ky, Reid, Bruce, Coffman, Samuel L., Hagen, Deborah A.
• Primary Examiner(s): Ngo; Hung V
• Application Number:
  US09/928,737
• Publication Number:
  US 20020053452A1
• Time in Patent Office: 3,536 Days
• Field of Search: 174/52.2, 174/521, 257/787, 257/788, 257/789, 257/790, 257/791, 257/792, 257/793, 257/794, 438/127, 438/462, 438/112, 438/460
• US Class Current: 438/137
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15787 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

A semiconductor package substrate (11) has an array of package sites (13, 14, 16, and 21) that are substantially identical. The entire array of package sites (13, 14, 16, and 21) is covered by an encapsulant (19). The individual package sites (13, 14, 16, and 21) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (11).

Claims

1. A method for making a packaged semiconductor device comprising:

providing an interconnect substrate having a plurality of substantially identical package sites arranged in an array, the plurality of sites being separated by a singulation space and the interconnect substrate being a ceramic substrate or a rigid printed circuit board substrate;

mounting and interconnecting a semiconductor device within each site;

forming a cavity containing the plurality of substantially identical package sites; and

overmolding a single and continuous encapsulant over each semiconductor device, the plurality of sites, and the singulation space, wherein overmolding produces a top surface of the continuous encapsulant which has a surface deviation of less than 0.13 millimeters across the top surface of the continuous encapsulant.

2. The method of claim 1 further comprising the step of singulating the plurality of package sites after overmolding.

3. The method of claim 2 wherein singulating comprises sawing through the single and continuous encapsulant and the interconnect substrate along the singulation space.

4. The method of claim 3 wherein singulating produces a plurality of packaged semiconductor devices, and further comprising the step of handling each packaged semiconductor device with automated pick and place equipment.

5. The method of claim 1, wherein forming a cavity comprises providing a dam-bar.

6. A method for making a packaged semiconductor device comprising:

providing an interconnect substrate that is either a ceramic substrate or a rigid printed circuit board substrate having a plurality of substantially identical package sites arranged in at least a four by four array, the plurality of sites being separated by a singulation space;

mounting and interconnecting a semiconductor device within each site;

forming a cavity containing the plurality of substantially identical package sites; and

overmolding a single and continuous encapsulant over each semiconductor device, the plurality of sites, and the singulation space to produce a top surface of the encapsulant which has a surface deviation of less than 0.13 millimeters across the top surface of the encapsulant.

7. The method of claim 6 further comprising the step of singulating the plurality of package sites after overmolding.

8. The method of claim 7 wherein singulating comprises sawing through the single and continuous encapsulant and the interconnect substrate along the singulation space.

9. The method of claim 8 wherein singulating produces a plurality of packaged semiconductor devices, and further comprising the step of handling each packaged semiconductor device with automated pick and place equipment.

10. The method of claim 6, wherein forming a cavity comprises providing a dam-bar.

11. A method for making a packaged semiconductor device comprising:

providing an interconnect substrate that is either a ceramic substrate or a rigid printed circuit board substrate having a plurality of substantially identical package sites arranged in an array, the plurality of sites being separated by a singulation space;

mounting and interconnecting a semiconductor device within each package site;

forming a cavity containing the plurality of substantially identical package sites; and

overmolding an encapsulant over the plurality of sites and the singulation space to have a top surface planarity deviation of less than 0.13 millimeters.

12. The method of claim 11 further comprising the step of singulating the plurality of package sites after overmolding.

13. The method of claim 12 wherein singulating comprises sawing through the single and continuous encapsulant and the interconnect substrate along the singulation space.

14. The method of claim 13 wherein singulating produces a plurality of packaged semiconductor devices, and further comprising the step of handling each packaged semiconductor device with automated pick and place equipment.

15. The method of claim 11, wherein forming a cavity comprises providing a dam-bar.