Devices with nanocrystals and methods of formation

• US 7,927,948 B2
• Filed: 07/20/2005
• Issued: 04/19/2011
• Est. Priority Date: 07/20/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S., Durcan, D. Mark
• Primary Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US11/185,113
• Publication Number:
  US 20070018342A1
• Time in Patent Office: 2,099 Days
• Field of Search: 438/257, 438/962, 257/315, 257/E29.3
• US Class Current: 438/257
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: Y10S 438/962 Quantum dots and lines

Abstract

An aspect relates to a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a surface of the substrate. The creation of the nucleation sites includes implanting ions with an energy and a dose selected to provide a controllable distribution of the nucleation sites across the surface of the substrate. Nanoscale structures are grown using the controllable distribution of nucleation sites to seed the growth of the nanoscale structures. According to various embodiments, the nanoscale structures include at least one of nanocrystals, nanowires and nanotubes. According to various nanocrystal embodiments, the nanocrystals are positioned within a gate stack and function as a floating gate for a nonvolatile device. Other aspects and embodiments are provided herein.

Claims

1. A method of growing nanoscale structures on a semiconductor substrate, comprising:

implanting the semiconductor substrate with ions at a selected energy and a selected dose such that a controlled distribution of nucleation sites embedded in a surface of an insulative layer is formed, the surface disposed away from an interface formed by the insulative layer disposed on the semiconductor substrate, implanted material of the ions in the surface being the nucleation sites arranged to seed growth of nanoscale structures; and

growing conductive nanoscale structures from the nucleation sites on the insulative layer by depositing material on the nucleation sites of the implanted material in the surface.

2. The method of claim 1, wherein implanting ions includes performing a plasma doping (PLAD) process.

3. The method of claim 1, wherein the implanted material of the implanted ions includes atomic elements that are also used in the conductive nanoscale structures.

4. The method of claim 1, wherein the implanted material of the implanted ions includes atomic elements different from elements comprising the conductive nanoscale structures.

5. The method of claim 1, wherein growing the conductive nanoscale structures includes performing an atomic layer deposition (ALD) process on the substrate with the nucleation sites.

6. The method of claim 1, wherein growing the conductive nanoscale structures includes performing a chemical vapor deposition (CVD) process on the substrate with the nucleation sites.

7. The method of claim 1, wherein growing the conductive nanoscale structures includes performing a physical vapor deposition (PVD) process on the substrate with the nucleation sites.

8. The method of claim 1, wherein growing the conductive nanoscale structures includes performing a spin coating process on the substrate with the nucleation sites.

9. The method of claim 1, wherein growing the conductive nanoscale structure includes growing a nanocrystal.

10. The method of claim 1, wherein growing the conductive nanoscale structure includes growing a nanowire.

11. The method of claim 1, wherein growing the conductive nanoscale structure includes growing a nanotube.

12. A method of growing nanocrystals on a semiconductor substrate, comprising:

implanting ions into a surface of an insulative layer, the surface disposed away from an interface formed by the insulative layer disposed on the semiconductor substrate, the ions implanted at a selected energy and a selected dose forming a controlled distribution of nucleation sites embedded in the surface, implanted material of the ions, implanted in the surface, being the nucleation sites arranged to seed growth of nanoscale structures; and

depositing material on the implanted material to grow conductive nanocrystals from the implanted material as nucleation sites on the insulative layer.

13. The method of claim 12, wherein implanting ions includes performing a plasma doping (PLAD) process.

14. The method of claim 12, wherein the energy and the dose are selected to provide nucleation sites with a desired distribution such that nanocrystal growth seeded by the nucleation sites provide charge storing nanocrystals.

15. The method of claim 14, wherein the charge storing nanocrystals are positioned within a gate stack to form a floating gate of a nonvolatile memory device.

16. The method of claim 14, wherein the charge storing nanocrystals are positioned within a transistor body of a nonvolatile memory device.

17. The method of claim 12, wherein the energy and the dose are selected to provide nucleation sites with a desired distribution such that nanocrystal growth seeded by the nucleation sites provide nanocrystals to enhance charge tunneling.

18. The method of claim 17, wherein the nanocrystals are positioned within a gate stack to enhance tunneling to and from a floating gate in a nonvolatile device.

19. The method of claim 12, wherein the energy and the dose are selected to provide nucleation sites with a desired distribution such that nanocrystals growth seeded by the nucleation sites provide nanocrystals to provide locally high current density.

20. The method of claim 12, wherein the conductive nanocrystals comprise a metal material.

21. The method of claim 12, wherein the conductive nanocrystals comprise a high work function material.

22. The method of claim 12, wherein the conductive nanocrystals comprise platinum (Pt).

23. The method of claim 12, wherein the conductive nanocrystals comprise rhodium (Rh).

24. The method of claim 12, wherein the conductive nanocrystals comprise ruthenium (Ru).

25. The method of claim 12, wherein the conductive nanocrystals comprise palladium (Pd).

26. The method of claim 12, wherein the conductive nanocrystals comprise cobalt (Co).

27. The method of claim 12, wherein the conductive nanocrystals comprise titanium (Ti).

28. The method of claim 12, wherein the conductive nanocrystals comprise zirconium (Zr).

29. The method of claim 12, wherein the conductive nanocrystals comprise hafnium (Hf).

30. The method of claim 12, wherein the conductive nanocrystals comprise tantalum (Ta).

31. The method of claim 12, wherein the conductive nanocrystals comprise tungsten (W).

32. The method of claim 12, wherein the conductive nanocrystals comprise tantalum nitride (TaN).

33. The method of claim 12, wherein the conductive nanocrystals comprise titanium nitride (TiN).

34. The method of claim 12, wherein the conductive nanocrystals comprise tungsten nitride (WN).