Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods

• US 7,928,425 B2
• Filed: 01/23/2008
• Issued: 04/19/2011
• Est. Priority Date: 01/25/2007
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Rao, Kalipatnam Vivek
• Primary Examiner(s): Sandvik; Benjamin P
• Assistant Examiner(s): KUO, WENSING W
• Application Number:
  US12/018,255
• Publication Number:
  US 20080179588A1
• Time in Patent Office: 1,182 Days
• Field of Search: 257/20, 257/E29.271, 257/E29.311, 257/E21.085, 438/570
• US Class Current: 257/20
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/154 comprising at least one long range structurally disordered material, e.g. one-dimensional vertical amorphous superlattices
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure

Abstract

A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

Claims

1. A semiconductor device comprising:

a semiconductor layer;

a superlattice interface layer on said semiconductor layer and coupled directly thereto; and

a metal layer on said superlattice interface layer and coupled directly thereto;

said superlattice interface layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

2. The semiconductor device of claim 1 wherein said semiconductor layer has spaced-apart source and drain regions therein defining a channel region therebetween;

and wherein said metal layer comprises a respective source metal contact for the source region and a drain metal contact for the drain region.

3. The semiconductor device of claim 2 further comprising a gate electrode layer overlying the channel region.

4. The semiconductor device of claim 3 wherein said superlattice interface layer extends beneath said gate electrode layer.

5. The semiconductor device of claim 3 further comprising a gate dielectric layer overlying the channel region and beneath said gate electrode layer.

6. The semiconductor device of claim 2 wherein said superlattice interface layer comprises a respective superlattice interface layer portion for each of said source and drain regions.

7. The semiconductor device of claim 1 wherein said metal layer comprises a plurality of stacked metal layers.

8. The semiconductor device of claim 1 wherein said metal layer comprises at least one of copper, aluminum, and ytterbium.

9. The semiconductor device of claim 1 wherein said superlattice interface layer has a thickness in a range of 3 to 10 Angstroms.

10. The semiconductor device of claim 1 wherein said semiconductor layer comprises a semiconductor-on-insulator (SOI) substrate.

11. The semiconductor device of claim 1 wherein said base semiconductor comprises silicon.

12. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises oxygen.

13. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

14. The semiconductor device of claim 1 wherein at least one group of layers of said superlattice interface layer is substantially undoped.

15. The semiconductor device of claim 1 wherein at least one group of layers of said superlattice interface layer is doped.

16. A semiconductor device comprising:

a semiconductor layer having spaced-apart source and drain regions therein defining a channel region therebetween;

a source metal contact coupled to the source region; and

a drain metal contact coupled to the drain region;

at least one superlattice interface layer coupled directly between the source region and said source contact, and coupled directly between the drain region and said drain contact;

said superlattice interface layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions, and wherein at least some silicon atoms from opposing base silicon portions are chemically bound together with the chemical bonds traversing the at least one intervening oxygen monolayer.

17. The semiconductor device of claim 16 further comprising a gate electrode layer overlying the channel region.

18. The semiconductor device of claim 17 wherein said at least one superlattice interface layer extends beneath said gate electrode layer.

19. The semiconductor device of claim 17 further comprising a gate dielectric layer overlying the channel region and beneath said gate electrode layer.

20. The semiconductor device of claim 16 wherein said at least one superlattice interface layer comprises a respective superlattice interface layer portion for each of said source and drain regions.

21. A method for making a semiconductor device comprising:

forming a superlattice interface layer on a semiconductor layer and coupled directly thereto; and

forming a metal layer on the superlattice interface layer and coupled directly thereto;

the superlattice interface layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

22. The method of claim 21 further comprising forming spaced-apart source and drain regions in the semiconductor layer defining a channel region therebetween;

and wherein forming the metal layer comprises forming a respective source metal contact for the source region and a drain metal contact for the drain region.

23. The method of claim 22 further comprising forming a gate electrode layer overlying the channel region.

24. The method of claim 23 wherein forming the gate electrode layer comprises forming the gate electrode layer overlying the superlattice interface layer.

25. The method of claim 22 wherein forming the superlattice interface layer comprises forming a respective superlattice interface layer portion for each of the source and drain regions.

26. The method of claim 22 further comprising forming a gate dielectric layer overlying the channel region and beneath the gate electrode layer.

27. The method of claim 21 wherein the base semiconductor comprises silicon, and wherein the at least one non-semiconductor monolayer comprises oxygen.