III-nitride light emitting device including porous semiconductor layer

• US 7,928,448 B2
• Filed: 12/04/2007
• Issued: 04/19/2011
• Est. Priority Date: 12/04/2007
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Philips Lumileds Lighting Company LLC (Apollo Global Management, Inc.)
• Inventors: Wierer, Jonathan J. Jr., Epler, John E.
• Primary Examiner(s): SAYADIAN, HRAYR
• Application Number:
  US11/950,211
• Publication Number:
  US 20090140274A1
• Time in Patent Office: 1,232 Days
• Field of Search: 257/13, 257/79, 257/94, 257/96, 257/97, 257/103, 257/E33.011, 257E33025-E33034, 257/E21.112, 257/E21.115, 257E21117-E21119, 257/E21.566
• US Class Current: 257/79
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body

Abstract

A semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown over a porous III-nitride region. A III-nitride layer comprising InN is disposed between the light emitting layer and the porous III-nitride region. Since the III-nitride layer comprising InN is grown on the porous region, the III-nitride layer comprising InN may be at least partially relaxed, i.e. the III-nitride layer comprising InN may have an in-plane lattice constant larger than an in-plane lattice constant of a conventional GaN layer grown on sapphire.

Claims

1. A device comprising:

a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region;

a porous III-nitride region comprising voids formed in a III-nitride material, the III-nitride material having a bulk lattice constant, defined as a lattice constant of a relaxed, free-standing material of the same composition as the III-nitride material; and

a III-nitride layer comprising InN touching the porous III-nitride region and disposed between the light emitting layer and the porous III-nitride region, the III-nitride layer comprising InN having a bulk lattice constant, defined as a lattice constant of a relaxed, free-standing material of the same composition as the III-nitride layer comprising InN;

wherein the bulk lattice constant of the III-nitride layer comprising InN is larger than the bulk lattice constant of the III-nitride material in the porous region.

2. The device of claim 1 wherein the porous III-nitride region is GaN.

3. The device of claim 1 wherein the porous III-nitride region comprises a plurality of voids formed in a GaN layer.

4. The device of claim 1 wherein at least 50% of a volume of the porous III-nitride region comprises voids.

5. The device of claim 1 wherein the porous III-nitride region is between 0.02 and 3 μ

m thick.

6. The device of claim 1 further comprising:

a mask layer disposed between the porous III-nitride region and the III-nitride layer comprising InN; and

a plurality of openings formed in the mask layer.

7. The device of claim 6 wherein the porous III-nitride region is divided into a plurality of regions, each of the plurality of porous regions being aligned with an opening in the mask layer.

8. The device of claim 1 wherein the III-nitride layer comprising InN has an in-plane lattice constant greater than 3.189 Å

.

9. The device of claim 1 further comprising first and second contacts electrically connected to the n-type and p-type regions.

10. The device of claim 1 further comprising a mount, wherein the semiconductor structure is connected to the mount by first and second contacts electrically connected to the n- and p-type regions, wherein the first and second contacts are both formed on a same side of the semiconductor structure.

11. The device of claim 1 wherein a volume percent of voids in a first portion of the porous III-nitride region is different from a volume percent of voids in a second portion of the porous III-nitride region.

12. A device comprising:

a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region; and

a porous III-nitride region disposed between first and second III-nitride regions;

wherein;

the second III-nitride region is touching the porous III-nitride region and disposed between the porous region and the light emitting layer;

a bulk lattice constant of the second III-nitride region is larger than a bulk lattice constant of the porous III-nitride region;

an in-plane lattice constant of the first III-nitride region is different from an in-plane lattice constant of the second III-nitride region; and

a difference between the in-plane lattice constant of the second III-nitride region and an in-plane lattice constant of the light emitting layer is smaller than a difference between the in-plane lattice constant of the first III-nitride region and the in-plane lattice constant of the light emitting layer.

13. The device of claim 12 wherein the first III-nitride region is GaN, the second III-nitride region is InGaN, and the porous region is GaN.

14. The device of claim 12 wherein the second III-nitride region is one of AlGaN, AlInN, and AlInGaN.

15. The device of claim 12 wherein the porous III-nitride region is between 0.02 and 3 μ

m thick.

16. The device of claim 12 further comprising:

a mask layer disposed between the porous III-nitride region and the first III-nitride region; and

a plurality of openings formed in the mask layer.

17. The device of claim 12 wherein a volume percent of voids in a first portion of the porous III-nitride region is different from a volume percent of voids in a second portion of the porous III-nitride region.