Nonvolatile semiconductor memory and manufacturing method thereof

• US 7,928,497 B2
• Filed: 09/13/2007
• Issued: 04/19/2011
• Est. Priority Date: 09/20/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yaegashi, Toshitake
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): NIESZ, JAMIE C
• Application Number:
  US11/854,845
• Publication Number:
  US 20080067576A1
• Time in Patent Office: 1,314 Days
• Field of Search: 257/316, 257/E29.3
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer.

Claims

1. A nonvolatile semiconductor memory comprising:

at least one memory cell and one peripheral transistor disposed on a semiconductor substrate,

the memory cell having;

a first gate insulating film provided on a first element area of the semiconductor substrate, the first element area being defined by a first isolation insulating layer provided on the semiconductor substrate;

a floating gate electrode provided on the first gate insulating film;

a first intergate insulating film having a multilayer structure and provided on the floating gate electrode and the isolation insulating layer; and

a control gate electrode provided on the first intergate insulating film,

the peripheral transistor having;

a second gate insulating film provided on a second element area of the semiconductor substrate, the second element area being defined by a second isolation insulating layer provided on the semiconductor substrate;

a first gate electrode provided on the second gate insulating film;

a second intergate insulating film having a multilayer structure and provided on the first gate electrode and the second isolation insulating layer; and

a second gate electrode provided on the second intergate insulating film,

wherein the first and the second intergate insulating films have the same multilayer structure, and a first insulating film serving as a lowermost layer of the first intergate insulating film contacting the first isolation insulating layer is thinner than a second insulating film serving as a lowermost layer of the second intergate insulating film contacting the second isolation insulating layer, and

a thickness of the first intergate insulating film excluding the first insulating film is the same as a thickness of the second intergate insulating film excluding the second insulating film.

2. The nonvolatile semiconductor memory according to claim 1, wherein the thickness at the end of the second insulating film on the second isolation insulating layer is smaller than the thickness in the center of the second insulating film on the second isolation insulating layer.

3. The nonvolatile semiconductor memory according to claim 1, wherein the first insulating film is thinner than a third insulating film serving as a lowermost layer of the first intergate insulating film contacting the floating gate electrode.

4. The nonvolatile semiconductor memory according to claim 1, wherein the size of the first gate electrode of the peripheral transistor is larger than the size of the floating gate electrode of the memory cell.

5. The nonvolatile semiconductor memory according to claim 1, wherein the first and second insulating films are silicon nitride films.

6. The nonvolatile semiconductor memory according to claim 1, wherein the first and second intergate insulating films having the multilayer structures include silicon nitride films and silicon oxide films.

7. The nonvolatile semiconductor memory according to claim 1, wherein the first and second intergate insulating films having the multilayer structures include silicon nitride films and high dielectric films.

17. The nonvolatile semiconductor memory according to claim 1, wherein the thickness at the end of the first insulating film on the first isolation insulating layer is the same thickness in the center of the first insulating film on the first isolation insulating layer.

8. A nonvolatile semiconductor memory comprising:

at least one memory cell and one peripheral transistor disposed on a semiconductor substrate,

the memory cell having;

a first gate insulating film provided on a first element area of the semiconductor substrate, the first element area being defined by a first isolation insulating layer provided on the semiconductor substrate;

a floating gate electrode provided on the first gate insulating film;

a first intergate insulating film having a multilayer structure and provided on the floating gate electrode and the isolation insulating layer; and

a control gate electrode provided on the first intergate insulating film,

the peripheral transistor having;

a second gate insulating film provided on a second element area of the semiconductor substrate, the second element area being defined by a second isolation insulating layer provided on the semiconductor substrate;

a first gate electrode provided on the second gate insulating film;

a second intergate insulating film having a multilayer structure and provided on the first gate electrode and the second isolation insulating layer; and

a second gate electrode provided on the second intergate insulating film,

wherein an insulating film serving as a lowermost layer of the second intergate insulating film contacts the second isolation insulating layer, does not contact the first isolation insulating layer, and contacts the floating gate electrode.

9. The nonvolatile semiconductor memory according to claim 8, wherein the thickness at the end of the insulating film serving as the lowermost layer of the second intergate insulating film contacting the second isolation insulating layer is smaller than the thickness in the center of the insulating film serving as the lowermost layer of the second intergate insulating film on the second isolation insulating layer.

10. The nonvolatile semiconductor memory according to claim 8, wherein the size of the first gate electrode of the peripheral transistor is larger than the size of the floating gate electrode of the memory cell.

11. The nonvolatile semiconductor memory according to claim 8, wherein the first and second intergate insulating films having the multilayer structures include silicon nitride films and silicon oxide films.

12. The nonvolatile semiconductor memory according to claim 11, wherein the silicon nitride film is in contact with the top of the second isolation layer.

13. The nonvolatile semiconductor memory according to claim 11, wherein the silicon oxide film is in contact with the top of the first isolation layer.

14. The nonvolatile semiconductor memory according to claim 8, wherein the first and second intergate insulating films having the multilayer structures include silicon nitride films and high dielectric films.

15. The nonvolatile semiconductor memory according to claim 14, wherein a silicon nitride film is in contact with the top of the second isolation layer.

16. The nonvolatile semiconductor memory according to claim 14, wherein a high dielectric film is in contact with the top of the first isolation layer.