Profile of flash memory cells

• US 7,928,499 B2
• Filed: 03/07/2007
• Issued: 04/19/2011
• Est. Priority Date: 03/07/2007
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lo, Chi-Hsin, Chang, Chu-Wei, Liu, Shih-Chang, Tsai, Chia-Shiung
• Primary Examiner(s): Bryant; Kiesha R
• Assistant Examiner(s): Anya; Igwe U
• Application Number:
  US11/715,229
• Publication Number:
  US 20080217675A1
• Time in Patent Office: 1,504 Days
• Field of Search: None
• US Class Current: 257/321
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a tunneling layer on the semiconductor substrate;

a source region adjacent the tunneling layer;

a floating gate on the tunneling layer, wherein the floating gate comprises;

a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion;

a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate; and

a control gate over the blocking layer, wherein the control gate comprises an edge facing the same direction as the first edge of the floating gate, and wherein the first edge of the blocking layer is recessed from the edge of the control gate.

2. The semiconductor structure of claim 1, wherein the first edge of the floating gate and the first edge of the blocking layer face the source region.

3. The semiconductor structure of claim 2, wherein the floating gate further comprises a second, a third, and a fourth edge not facing the source region, and wherein the second, the third and the fourth edges are substantially vertical.

4. The semiconductor structure of claim 2 further comprising:

an additional tunneling layer on the semiconductor substrate, wherein the additional tunneling layer is adjacent to the source region;

an floating gate on the additional tunneling layer, wherein the additional floating gate has a first edge facing the source region; and

an additional blocking layer on the additional floating gate, wherein the additional blocking layer has a first edge facing the source region, and wherein the first edge of the additional floating gate has at least a lower portion recessed from an upper portion.

5. The semiconductor structure of claim 1 further comprising:

an inter-poly oxide on the source region;

an erase gate on the inter-poly oxide; and

a word-line on an opposite side of the floating gate than the erase gate.

6. The semiconductor structure of claim 1, wherein the lower portion of the first edge of the floating gate is recessed from the first edge of the blocking layer.

7. The semiconductor structure of claim 1, wherein the lower portion is more recessed than the upper portion for a distance of greater than a 10 percent of a width of the floating gate.

8. The semiconductor structure of claim 1, wherein the upper portion of the first edge of the floating gate is recessed from the first edge of the blocking layer for a distance of greater than 10 percent of a width of the floating gate.

9. A semiconductor structure comprising:

a semiconductor substrate;

a first tunneling layer and a second tunneling layer on the semiconductor substrate;

a common source region between the first and the second tunneling layers, wherein the common source region is in the semiconductor substrate;

a first floating gate on the first tunneling layer, wherein the first floating gate has a first sidewall facing the common source region, and wherein a lower portion of the first sidewall of the first floating gate is recessed from an upper portion;

a second floating gate on the second tunneling layer, wherein the second floating gate has a first sidewall facing the common source region, and wherein a lower portion of the first sidewall of the second floating gate is recessed from an upper portion;

a first blocking layer over the first floating gate, wherein the first blocking layer has a sidewall facing the common source region; and

a first control gate over the first blocking layer, wherein the first control gate has a sidewall facing the common source region, and wherein the sidewall of the first blocking layer is recessed from the sidewall of the first control gate.

10. The semiconductor structure of claim 9 further comprising a second blocking layer on the second floating gate, wherein the first and the second floating gates each have a tip substantially adjoining the first and the second blocking layers, respectively.

11. The semiconductor structure of claim 10 further comprising a common erase gate between the first and the second floating gates.

12. The semiconductor structure of claim 11, wherein the tips of the first and the second floating gates point to the common erase gate.

13. The semiconductor structure of claim 9, wherein each of the first and the second floating gates further comprises a second, a third and a fourth sidewall not facing the common source region, and wherein the second, the third and the fourth sidewalls of each of the first and the second floating gates are substantially vertical.

14. The semiconductor structure of claim 9, wherein the lower portion of the sidewall of the first floating gate is recessed from the upper portion by a distance of greater than about 10 percent of a width of the first floating gate.

15. A semiconductor structure comprising:

a semiconductor substrate;

a first active region in the semiconductor substrate;

a second active region in the semiconductor substrate, wherein the first and the second active regions are parallel and spaced apart by an insulation region;

a connecting active region perpendicular to the first and the second active regions and connecting a portion of the first active region to a portion of the second active region;

a first tunneling layer on the first active region;

a first floating gate on the first tunneling layer, wherein the first floating gate has a first edge facing the connecting active region, and wherein a bottom portion of the first edge is recessed from a top portion of the first edge;

a second tunneling layer on the second active region;

a second floating gate on the second tunneling layer, wherein the first and the second floating gates are disconnected from each other, and wherein the second floating gate has a second edge facing the connecting active region, and wherein a bottom portion of the second edge is recessed from a top portion of the second edge;

a blocking layer extending from over the first floating gate to over the second floating gate; and

a control gate layer on the blocking layer, the control gate layer extending from over the first floating gate to over the second floating gate, wherein each of the blocking layer and the control gate layer comprises an edge facing the connecting active region, and wherein the edge of the blocking layer is recessed from the edge of the control gate layer.

16. The semiconductor structure of claim 15, wherein the blocking layer extends substantially over an edge of the connecting active region, and wherein the first and the second edges of the respective first and the second floating gates are spaced apart from the edge of the connecting active region.