Semiconductor device with vertical trench and lightly doped region

• US 7,928,505 B2
• Filed: 12/02/2008
• Issued: 04/19/2011
• Est. Priority Date: 12/03/2007
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Hirao, Takashi, Hashimoto, Takayuki, Akiyama, Noboru
• Primary Examiner(s): Pham; Hoai V
• Application Number:
  US12/326,392
• Publication Number:
  US 20090140327A1
• Time in Patent Office: 868 Days
• Field of Search: 257/135, 257/302, 257/330, 257/331, 257/332, 257/333, 257/E27.091
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The vertical trench MOSFET comprises: an N type epitaxial region formed on an upper surface of an N⁺ type substrate having a drain electrode on a lower surface thereof; a gate trench extending from a front surface into the N type epitaxial region; a gate electrode positioned in the gate trench so as to interpose an insulator; a channel region formed on the N type epitaxial region; a source region formed on the channel region; a source electrode formed on the source region; a source trench extending from the front surface into the N type epitaxial region; and a trench-buried source electrode positioned in the source trench so as to interpose an insulator, wherein the source electrode contacts with the trench-buried source electrode.

Claims

1. A semiconductor device comprising:

a first semiconductor region of a first conductivity type formed on an upper surface of a semiconductor substrate having a rear surface electrode on a lower surface thereof;

a gate trench extending from a front surface of the semiconductor device into the first semiconductor region;

a gate electrode positioned in the gate trench so as to interpose an insulator;

a second semiconductor region of a second conductivity type formed on the first semiconductor region and adjacent to the gate trench;

a third semiconductor region of the first conductivity type formed on the second semiconductor region and adjacent to the gate trench;

a field electrode formed on the third semiconductor region;

a field trench extending from the front surface of the semiconductor device into the first semiconductor region;

a trench-buried field electrode positioned in the field trench so as to interpose an insulator; and

a fourth semiconductor region that is less doped than the first semiconductor region and of the first conductivity type, where the fourth semiconductor region is disposed in the first semiconductor region under the field trench,

wherein the field electrode contacts with the trench-buried field electrode.

2. The semiconductor device according to claim 1,

wherein a distance from the front surface of the semiconductor device to a bottom of the field trench is longer than that from the front surface of the semiconductor device to a bottom of the gate trench.

3. The semiconductor device according to claim 1,

wherein the field electrode contacts with the second semiconductor region in the field trench or contacts with a more highly-doped body contact region that the second semiconductor region, the body contact region being of second conductivity type and contacting with the second semiconductor region.

4. The semiconductor device according to claim 1,

wherein a distance from the front surface of the semiconductor device to a bottom of the gate trench is equal to that from the front surface of the semiconductor device to a bottom of the field trench.

5. The semiconductor device according to claim 4,

wherein an insulator of a bottom surface in the gate trench is thicker than an insulator of a side surface in the gate trench.

6. The semiconductor device according to claim 5,

wherein a thickness of the insulator of the bottom surface in the gate trench is larger than a distance from an interface between the first semiconductor region and the second semiconductor region to the insulator of the bottom surface in the gate trench.

7. The semiconductor device according to claim 1,

wherein a more highly-doped body contact region than the second semiconductor region, the body contact region being of second conductivity type, is selectively formed on a front surface of the second semiconductor region.

8. The semiconductor device according to claim 1,

wherein a bottom of the field trench reaches an inside of the semiconductor substrate.

9. The semiconductor device according to claim 1,

wherein the gate trench and the field trench are in parallel relationship to each other.

10. The semiconductor device according to claim 9,

wherein the gate trench and the field trench are alternately positioned to each other.

11. The semiconductor device according to claim 1,

wherein the trench-buried field electrode is poly-silicon.

12. A semiconductor device comprising:

a first semiconductor region of a first conductivity type formed on an upper surface of a semiconductor substrate having a rear surface electrode on a lower surface thereof;

a second semiconductor region of a second conductivity type selectively formed on a front surface of the first semiconductor region;

a third semiconductor region of the first conductivity type selectively formed on a front surface of the second semiconductor region;

a gate electrode positioned on the second semiconductor region so as to interpose an insulator;

a field electrode formed on the third semiconductor region;

a field trench extending from a front surface of a semiconductor device into the first semiconductor region;

a trench-buried field electrode positioned in the field trench so as to interpose an insulator; and

a fourth semiconductor region that is less doped than the first semiconductor region and of the first conductivity type, where the fourth semiconductor region is disposed in the first semiconductor region under the field trench,

wherein the field electrode contacts with the trench-buried field electrode.

13. The semiconductor device according to claim 12,

wherein the field electrode contacts with the second semiconductor region in the field trench or contacts with a more highly-doped body contact region than the second semiconductor region, the body contact region being of second conductivity type and contacting with the second semiconductor region.

14. The semiconductor device according to claim 12,

wherein a more highly-doped body contact region than the second semiconductor region, the body contact region being of second conductivity type, is selectively formed on the front surface of the second semiconductor region.

15. The semiconductor device according to claim 12,

wherein a bottom of the field trench reaches an inside of the semiconductor substrate.

16. The semiconductor device according to claim 12,

wherein the trench-buried field electrode is poly-silicon.