Lead frame for semiconductor package

• US 7,928,542 B2
• Filed: 03/06/2009
• Issued: 04/19/2011
• Est. Priority Date: 03/27/2001
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Lee, Hyung Ju
• Primary Examiner(s): Luu; Chuong A.
• Application Number:
  US12/399,600
• Publication Number:
  US 20090166842A1
• Time in Patent Office: 774 Days
• Field of Search: 257/666, 257/670, 257/669, 257/712, 257/690, 257/676, 257/692, 257/693
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48253 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85455 Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/85464 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/8547 Zirconium (Zr) as principal constituent
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

Claims

1. A semiconductor package, comprising:

a die pad;

a ground ring extending at least partially about the die pad and defining;

a generally planar first ground ring surface;

a generally planar second ground ring surface disposed in opposed relation to the first ground ring surface; and

at least one third ground ring surface formed between the first and second ground ring surfaces in opposed relation to the first ground ring surface; and

a plurality of leads extending at least partially about the ground ring in spaced relation thereto;

a semiconductor chip attached to the die pad and electrically connected to at least some of the leads and to the first ground ring surface of the ground ring; and

a sealing part at least partially encapsulating the die pad, the ground ring, the leads, and the semiconductor chip such that the second ground ring surface of the ground ring is exposed.

2. The semiconductor package of claim 1 wherein the die pad defines:

a generally planar first die pad surface;

a generally planar second die pad surface disposed in opposed relation to the first die pad surface; and

a third die pad surface formed between the first and second die pad surfaces in opposed relation to the first die pad surface and at least partially circumventing the second die pad surface.

3. The semiconductor package of claim 2 wherein:

the semiconductor chip is attached to the first die pad surface of the die pad; and

the sealing part partially encapsulates the die pad such that the second die pad surface of the die pad is exposed.

4. The semiconductor package of claim 1 wherein each of the leads defines:

a generally planar first lead surface;

a generally planar second lead surface disposed in opposed relation to the first lead surface; and

a third lead surface formed between the first and second third lead surfaces in opposed relation to the first lead surface, the third lead surface being disposed closer to the ground ring than the second lead surface;

the sealing part partially encapsulating the leads such that the second lead surface of each of the leads is exposed.

5. The semiconductor package of claim 1 further comprising at least two tie bars which are each connected to and extend between the die pad and the ground ring, and each define:

a generally planar first tie bar surface;

a generally planar second tie bar surface disposed in opposed relation to the first tie bar surface; and

a third tie bar surface formed between the first and second tie bar surfaces in opposed relation to the first tie bar surface;

the sealing part partially encapsulating the tie bars such that the second tie bar surface of each of the tie bars is exposed.

6. The semiconductor package of claim 1 wherein the ground ring defines at least two third ground ring surfaces separated by the second ground ring surface.

7. The semiconductor package of claim 1 wherein:

the semiconductor chip is electrically connected to respective ones of the leads and the first ground ring surface of the ground ring via conductive wires; and

the conductive wires are encapsulated with the sealing part.

8. The semiconductor package of claim 7 wherein at least one of the conductive wires is bonded to a portion of the first ground ring surface disposed in opposed relation to the second ground ring surface.

9. The semiconductor package of claim 1 wherein:

the die pad has a generally quadrangular configuration defining four peripheral edge segments;

the ground ring is segregated into four segments which extend along and are spaced from respective ones of the peripheral edge segments of the die pad; and

the leads are segregated into four sets which extend toward respective ones of the segments of the ground ring.

10. A semiconductor package, comprising:

a die pad having at least one portion that is partially etched;

a ground ring extending at least partially about the die pad and having portions that are partially etched;

a plurality of leads extending at least partially about the ground ring in spaced relation thereto;

a semiconductor chip attached to the die pad and electrically connected to at least some of the leads and to a first ground ring surface of the ground ring; and

a sealing part at least partially encapsulating the die pad, the ground ring, the leads, and the semiconductor chip.

11. The semiconductor package of claim 10 wherein the die pad defines:

a generally planar first die pad surface;

a generally planar second die pad surface disposed in opposed relation to the first die pad surface; and

a third die pad surface formed between the first and second die pad surfaces in opposed relation to the first die pad surface and at least partially circumventing the second die pad surface.

12. The semiconductor package of claim 11 wherein:

the semiconductor chip is attached to the first die pad surface of the die pad; and

the sealing part partially encapsulates the die pad such that the second die pad surface of the die pad is exposed.

13. The semiconductor package of claim 10 wherein each of the leads defines:

a generally planar first lead surface;

a generally planar second lead surface disposed in opposed relation to the first lead surface; and

a third lead surface formed between the first and second third lead surfaces in opposed relation to the first lead surface, the third lead surface being disposed closer to the ground ring than the second lead surface;

the sealing part partially encapsulating the leads such that the second lead surface of each of the leads is exposed.

14. The semiconductor package of claim 10 further comprising at least two tie bars which are each connected to and extend between the die pad and the ground ring, and each define:

a generally planar first tie bar surface;

a generally planar second tie bar surface disposed in opposed relation to the first tie bar surface; and

a third tie bar surface formed between the first and second tie bar surfaces in opposed relation to the first tie bar surface;

the sealing part partially encapsulating the tie bars such that the second tie bar surface of each of the tie bars is exposed.

15. The semiconductor package of claim 14 wherein the ground ring is separated from the die pad by at least one elongate slot.

16. The semiconductor package of claim 14 wherein:

the die pad has a generally quadrangular configuration defining four peripheral edge segments;

the ground ring is segregated into four segments which extend along and are spaced from respective ones of the peripheral edge segments of the die pad by elongate slots; and

the leads are segregated into four sets which extend toward respective ones of the segments of the ground ring.

17. The semiconductor package of claim 10 wherein the ground ring defines at least two third ground ring surfaces which are disposed in opposed relation to the first ground ring surface, and are separated by a second ground ring surface which is also disposed in opposed relation to the first ground ring surface, the sealing part partially encapsulating the ground ring such that the second ground ring surface is exposed.

18. The semiconductor package of claim 17 wherein:

the semiconductor chip is electrically connected to respective ones of the leads and the first ground ring surface of the ground ring via conductive wires; and

the conductive wires are encapsulated with the sealing part.

19. The semiconductor package of claim 18 wherein at least one of the conductive wires is bonded to a portion of the first ground ring surface disposed in opposed relation to the second ground ring surface.

20. A semiconductor package, comprising:

a die pad;

a ground ring extending at least partially about the die pad and having portions that are partially etched;

a plurality of leads extending at least partially about the ground ring in spaced relation thereto;

a semiconductor chip attached to the die pad and electrically connected to at least some of the leads and to a first ground ring surface of the ground ring; and

a sealing part at least partially encapsulating the die pad, the ground ring, the leads, and the semiconductor chip such that a second ground ring surface of the ground ring which is disposed in opposed relation to the first ground ring surface and portions of the leads are exposed in a common surface of the sealing part.