Post passivation interconnection schemes on top of the IC chips

• US 7,928,576 B2
• Filed: 01/25/2008
• Issued: 04/19/2011
• Est. Priority Date: 10/15/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Picardat; Kevin M
• Application Number:
  US12/019,635
• Publication Number:
  US 20080116581A1
• Time in Patent Office: 1,180 Days
• Field of Search: 257/690, 257/691, 257/700, 257/773, 257/774, 257/E21.575, 438614-616, 438/622, 438/631, 438/637, 438/638, 438/107, 438/110, 438/624
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01007 Nitrogen [N]
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A chip structure comprising:

a silicon substrate;

a first internal circuit in and on said silicon substrate;

a second internal circuit in and on said silicon substrate;

a first intra-chip driver or receiver in and on said silicon substrate;

a second intra-chip driver or receiver in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure connects a first terminal of said first intra-chip driver or receiver to said first internal circuit;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure connects a first terminal of said second intra-chip driver or receiver to said second internal circuit;

a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a second terminal of said first intra-chip driver or receiver;

a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to a second terminal of said second intra-chip driver or receiver;

a passivation layer over said dielectric layer, wherein said passivation layer comprises nitride layer; and

a fifth interconnecting structure over said passivation layer, wherein said second terminal of said first intra-chip driver or receiver is connected to said second terminal of said second intra-chip driver or receiver through, in sequence, said third interconnecting structure, said fifth interconnecting structure and said fourth interconnecting structure.

2. The chip structure of claim 1, wherein said fifth interconnecting structure comprises a data-signal line connecting said second terminal of said first intra-chip driver or receiver to said second terminal of said second intra-chip driver or receiver.

3. The chip structure of claim 1, wherein said fifth interconnecting structure comprises a logic-signal line connecting said second terminal of said first intra-chip driver or receiver to said second terminal of said second intra-chip driver or receiver.

4. The chip structure of claim 1, wherein said fifth interconnecting structure comprises a clock line connecting said second terminal of said first intra-chip driver or receiver to said second terminal of said second intra-chip driver or receiver.

5. The chip structure of claim 1, wherein said fifth interconnecting structure comprises electroplated copper.

6. The chip structure of claim 1, wherein said fifth interconnecting structure comprises electroplated gold.

7. The chip structure of claim 1, wherein said fifth interconnecting structure comprises an electroplated metal.

8. The chip structure of claim 1, wherein said fifth interconnecting structure comprises a line of a power voltage output from a voltage regulator, wherein said line connects said second terminal of said first intra-chip driver or receiver to said second terminal of said second intra-chip driver or receiver.

9. The chip structure of claim 1 further comprising an off-chip driver, receiver or I/O circuit in and on said silicon substrate, a sixth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said sixth interconnecting structure is connected to a first terminal of said off-chip driver, receiver or I/O circuit, a seventh interconnecting structure over said silicon substrate and in said dielectric layer, wherein said seventh interconnecting structure is connected to a second terminal of said off-chip driver, receiver or I/O circuit, and an external pad over said silicon substrate, wherein said external pad is connected to said second terminal of said off-chip driver, receiver or I/O circuit through said seventh interconnecting structure, wherein said first terminal of said off-chip driver, receiver or I/O circuit is connected to said second terminal of said first intra-chip driver or receiver through, in sequence, said sixth interconnecting structure, said fifth interconnecting structure and said third interconnecting structure, and wherein said first terminal of said off-chip driver, receiver or I/O circuit is connected to said second terminal of said second intra-chip driver or receiver through, in sequence, said sixth interconnecting structure, said fifth interconnecting structure and said fourth interconnecting structure.

10. The chip structure of claim 9 further comprising an ESD circuit in and on said silicon substrate, wherein said ESD circuit is connected to said external pad and to said second terminal of said off-chip driver, receiver or I/O circuit through said seventh interconnecting structure.

11. The chip structure of claim 1 further comprising a polymer layer comprising a portion over said fifth interconnecting structure.

12. A chip structure comprising:

a silicon substrate;

an internal circuit in and on said silicon substrate;

an intra-chip driver or receiver in and on said silicon substrate;

an off-chip driver, receiver or I/O circuit in and on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure connects a first terminal of said intra-chip driver or receiver to said internal circuit;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to a second terminal of said intra-chip driver or receiver;

a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a first terminal of said off-chip driver, receiver or I/O circuit;

a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to a second terminal of said off-chip driver, receiver or I/O circuit;

a passivation layer over said dielectric layer;

a fifth interconnecting structure over said passivation layer, wherein said first terminal of said off-chip driver, receiver or I/O circuit is connected to said second terminal of said intra-chip driver or receiver through, in sequence, said third interconnecting structure, said fifth interconnecting structure and said second interconnecting structure; and

an external pad over said silicon substrate, wherein said external pad is connected to said second terminal of said off-chip driver, receiver or I/O circuit through said fourth interconnecting structure.

13. The chip structure of claim 12, wherein said fifth interconnecting structure comprises a data-signal line connecting said first terminal of said off-chip driver, receiver or I/O circuit to said second terminal of said intra-chip driver or receiver.

14. The chip structure of claim 12, wherein said fifth interconnecting structure comprises electroplated copper.

15. The chip structure of claim 12, wherein said fifth interconnecting structure comprises electroplated gold.

16. The chip structure of claim 12, wherein said fifth interconnecting structure comprises an electroplated metal.

17. The chip structure of claim 12, wherein said fifth interconnecting structure comprises a line of a power voltage output from a voltage regulator, wherein said line connects said first terminal of said off-chip driver, receiver or I/O circuit to said second terminal of said intra-chip driver or receiver.

18. The chip structure of claim 12 further comprising an ESD circuit in and on said silicon substrate, wherein said ESD circuit is connected to said external pad and to said second terminal of said off-chip driver, receiver or I/O circuit through said fourth interconnecting structure.

19. The chip structure of claim 12 further comprising a polymer layer comprising a portion over said fifth interconnecting structure.

20. The chip structure of claim 12, wherein said fifth interconnecting structure comprises a clock line connecting said first terminal of said off-chip driver, receiver or I/O circuit to said second terminal of said intra-chip driver or receiver.

26. The chip structure of claim 12, wherein said passivation layer comprises a nitride layer.

21. A chip structure comprising:

a silicon substrate;

a transistor on said silicon substrate;

a first dielectric layer over said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer and said silicon substrate;

a second dielectric layer between said first and second metal layers;

a first metal interconnect over said silicon substrate;

a second metal interconnect over said silicon substrate;

a third metal interconnect over said silicon substrate and between said first and second metal interconnects, wherein said third metal interconnect has a portion spaced apart from said first metal interconnect and from said second metal interconnect;

a passivation layer over said first and second metal layers, said first and second dielectric layers and said first, second and third metal interconnects, wherein said first, second and third metal interconnects are provided by a topmost metal layer under said passivation layer, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride layer;

a third metal layer over said passivation layer, over said third metal interconnect and on said first and second contact points, wherein said portion of said third metal interconnect is vertically under said third metal layer, wherein said passivation layer comprises a portion between said third metal layer and said third metal interconnect, wherein said first contact point is connected to said second contact point through said third metal layer, wherein said third metal layer comprises electroplated copper;

a first polymer layer over said passivation layer and said third metal layer, wherein a third opening in said first polymer layer is over a third contact point of said third metal layer, wherein said third contact point is not vertically over said first and second openings, wherein said first polymer layer has a thickness between 2 and 150 micrometers; and

a fourth metal layer on said first polymer layer, on said third contact point and vertically over said first and second contact points, wherein said fourth metal layer comprises a piece of metal on said first polymer layer, on said third contact point and vertically over said first and second contact points, wherein said piece of metal is connected to said third contact point through said third opening, wherein said piece of metal is connected to said first contact point through said third metal layer, and wherein said piece of metal is connected to said second contact point through said third metal layer.

22. The chip structure of claim 21 further comprising a second polymer layer on said passivation layer, wherein said third metal layer is further on said second polymer layer.

23. The chip structure of claim 21 further comprising a second polymer layer over said fourth metal layer.

24. The chip structure of claim 21, wherein said passivation layer further comprises an oxide layer.

25. The chip structure of claim 21, wherein said nitride layer has a thickness greater than 0.4 micrometers.

35. The chip structure of claim 21, wherein said first metal interconnect has a portion spaced apart from said portion of said third metal interconnect, wherein said second metal interconnect has a portion spaced apart from said portion of said third metal interconnect, wherein said portion of said first metal interconnect is spaced apart from said portion of said second metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point.

27. A chip structure comprising:

a silicon substrate;

a transistor on said silicon substrate;

a first dielectric layer over said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer and said silicon substrate;

a second dielectric layer between said first and second metal layers;

a first metal interconnect over said silicon substrate;

a second metal interconnect over said silicon substrate;

a third metal interconnect over said silicon substrate and between said first and second metal interconnects, wherein said third metal interconnect has a portion spaced apart from said first metal interconnect and from said second metal interconnect;

a separating layer over said first and second metal layers, over said first and second dielectric layers and on said third metal interconnect, wherein said first, second and third metal interconnects are provided by a topmost metal layer under said separating layer, wherein a first opening in said separating layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening;

a third metal layer over said separating layer, over said third metal interconnect and on said first and second contact points, wherein said portion of said third metal interconnect is vertically under said third metal layer, wherein said separating layer comprises a portion between said third metal layer and said third metal interconnect, wherein said first contact point is connected to said second contact point through said third metal layer, wherein said third metal layer comprises electroplated copper;

a first polymer layer over said separating layer and over a top surface of said third metal layer, wherein said first polymer layer covers said top surface of said third metal layer and a sidewall of said third metal layer, wherein a third opening in said first polymer layer is over a third contact point of said top surface of said third metal layer, wherein said third contact point is not vertically over said first and second openings, wherein said first polymer layer has a thickness between 2 and 150 micrometers; and

a fourth metal layer on said first polymer layer, on said third contact point and vertically over said first and second contact points, wherein said fourth metal layer comprises a piece of metal on said first polymer layer, on said third contact point and vertically over said first and second contact points, wherein said piece of metal is connected to said third contact point through said third opening, wherein said piece of metal is connected to said first contact point through said third metal layer, and wherein said piece of metal is connected to said second contact point through said third metal layer.

28. The chip structure of claim 27 further comprising a second polymer layer on said separating passivation layer, wherein said third metal layer is further on said second polymer layer.

29. The chip structure of claim 27 further comprising a second polymer layer over said fourth metal layer.

30. The chip structure of claim 27, wherein said separating layer comprises a nitride layer.

36. The chip structure of claim 27, wherein said first metal interconnect has a portion spaced apart from said portion of said third metal interconnect, wherein said second metal interconnect has a portion spaced apart from said portion of said third metal interconnect, wherein said portion of said first metal interconnect is spaced apart from said portion of said second metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point.

31. A chip structure comprising:

a silicon substrate;

a transistor on said silicon substrate;

a first dielectric layer over said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer and over said silicon substrate;

a second dielectric layer between said first and second metal layers;

a first metal interconnect over said silicon substrate;

a second metal interconnect over said silicon substrate, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect;

a separating layer over said first and second metal layers and over said first and second dielectric layers, wherein said first and second metal interconnects are provided by a topmost metal layer under said separating layer, wherein a first opening in said separating layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, wherein said separating layer comprises a nitride layer having a thickness greater than 0.4 micrometers;

a third metal layer over said separating layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said third metal layer, wherein said third metal layer comprises electroplated copper;

a first polymer layer over said separating layer and said third metal layer, wherein a third opening in said first polymer layer is over a third contact point of said third metal layer, wherein said third contact point is not vertically over said first and second openings, wherein said first polymer layer has a thickness between 2 and 150 micrometers; and

a fourth metal layer on said first polymer layer, on said third contact point and vertically over said first and second contact points, wherein said fourth metal layer comprises a piece of metal on said first polymer layer, on said third contact point and vertically over said first and second contact points, wherein said piece of metal is connected to said third contact point through said third opening, wherein said piece of metal is connected to said first contact point through said third metal layer, and wherein said piece of metal is connected to said second contact point through said third metal layer.

32. The chip structure of claim 31 further comprising a second polymer layer on said separating layer, wherein said third metal layer is further on said second polymer layer.

33. The chip structure of claim 31 further comprising a second polymer layer over said fourth metal layer.

34. The chip structure of claim 31, wherein said second metal interconnect has a portion spaced apart from said portion of said first metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point.