Synchronous light emitting diode lamp string controller

• US 7,928,667 B2
• Filed: 11/21/2007
• Issued: 04/19/2011
• Est. Priority Date: 11/23/2006
• Status: Active Grant

• Current Assignee: Semisilicon Technology Corp.
• Original Assignee: Semisilicon Technology Corp.
• Inventors: Peng, Jacky
• Primary Examiner(s): Owens; Douglas W
• Assistant Examiner(s): Le; Tung X
• Application Number:
  US11/984,697
• Publication Number:
  US 20090273303A1
• Time in Patent Office: 1,245 Days
• Field of Search: 315178-184, 315/185.R, 315/185.S, 315/200.R, 315/291, 315/294, 315/297, 315/312, 362/227, 362/251, 362/555, 362564-566, 362/640, 362/644, 362652-654, 362/800, 362/806
• US Class Current: 315/294
• CPC Class Codes: H05B 45/30 Driver circuits
• CPC Class Codes: H05B 45/345 Current stabilisation; Maintaining constant current

Abstract

The present invention discloses a synchronous LED lamp string controller, comprising a clock synchronous circuit to receive a reference signal with a constant frequency, and based on which, to generate a system clock; a counter circuit to counter the system clock and generate a clock signal; a control logic circuit to receive said clock signal to generate a control signal; and a driver circuit to receive said control signal to drive at least a light emitting diode.

Claims

1. A synchronous LED lamp string controller, comprising

a recognition circuit for receiving a reference signal with a constant frequency to carry out level shift and voltage biasing and output a recognition signal;

a shift register for receiving and storing the recognition signal;

an encoder circuit for receiving the data stored in the shift register and encoding and outputting said data;

a register for receiving and storing the complete data stored in the shift register; and

a driver circuit for receiving the data stored in the register to drive at least a light emitting diode.

2. The synchronous LED lamp string controller according to claim 1, wherein the recognition circuit uses a capacitor to filter the direct current value of said reference signal and retain the alternate current value, uses a bias resistor to bias the filtered reference signal within the working voltage range of the synchronous LED lamp string controller, uses two voltage comparators each connected with a reference voltage level for comparison with the biased reference signal, and outputs a recognition signal representing the reference signal level being higher than the two reference voltage levels, lower than the two reference voltage levels, or lying between the two reference voltage levels.

3. The synchronous LED lamp string controller according to claim 1, wherein the encoder circuit has an output buffer and a bias resistor, the output power of the output buffer being higher than the output power of said bias resistor, the encoder circuit receiving the data stored in the shift register and outputting the same data via the output buffer, biasing the data output by the output buffer within the working voltage range of the synchronous LED lamp string controller via the bias resistor, and outputting the biased data.

4. A synchronous LED lamp string controller, comprising

a first control logic circuit coupled to a data input pin;

and

a second control logic circuit coupled to a data output pin;

wherein data logic H in one bit transmitted by the data input pin and the data output pin is represented by a first voltage level with a predefined time interval and a second voltage level thereafter in one bit, data logic L in one bit transmitted by the data input pin and the data output pin is represented by a third voltage level with the predefined time interval and the second voltage level thereafter in one bit, the second voltage level is between the first voltage level and the third voltage level; and

wherein the data input pin and the output pin transmit data with same clock.

5. A synchronous LED lamp string controller, comprising

a first control logic circuit coupled to a data input pin;

and

a second control logic circuit coupled to a data output pin;

wherein data logic H in one bit transmitted by the data input pin and the data output pin is represented by a first voltage level with a first predefined time interval and a second voltage level thereafter in one bit, data logic L in one bit transmitted by the data input pin and the data output pin is represented by a first voltage level with a second predefined time interval and the second voltage level thereafter in one bit; and

wherein the data input pin and the output pin transmit data with same clock.