Method and system for texture block swapping memory management

• US 7,928,988 B1
• Filed: 11/19/2004
• Issued: 04/19/2011
• Est. Priority Date: 11/19/2004
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Levas, Menelaos
• Primary Examiner(s): Tung; Kee M
• Assistant Examiner(s): CRAWFORD, JACINTA M
• Application Number:
  US10/993,640
• Time in Patent Office: 2,342 Days
• Field of Search: 345/557, 345/582, 345/538, 345/544
• US Class Current: 345/537
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/04 Texture mapping

Abstract

A method and system for implementing transfers of texture data in a computer system. The method includes the step of accessing a first block of texture data in a low latency memory, the first block having a predetermined size and accessing a second block of texture data in high latency memory, the second block having the predetermined size. The first block of texture data is copied from the low latency memory to a transfer space in high latency memory having the predetermined size. The second block of texture data is written from the high latency memory to the low latency memory, wherein the second block overwrites the first block. What used to be the transfer space is now treated as the first block now placed in high latency memory, and what used to be the second block is now treated to be the new transfer space.

Claims

1. A method to implement transfers of texture data in a computer system, comprising:

accessing a first block of texture data in a low latency memory, the first block having a predetermined size corresponding to a size of texture stored in said first block of texture data;

accessing a second block of texture data in high latency memory, the second block having the predetermined size based on a size of said first block of texture data;

copying the first block of texture data from the low latency memory to a transfer space in high latency memory having the predetermined size, wherein the transfer space is allocated to accommodate a block of texture data of the predetermined size, wherein said transfer space is in a location separate from said first block of texture data and said second block of texture data;

writing the second block of texture data from the high latency memory to the low latency memory, wherein the second block overwrites the first block; and

accessing what used to be the transfer space as the first block in high latency memory, wherein what used to be the second block is accessed as a new transfer space.

2. The method of claim 1, wherein a plurality of transfer spaces are configured with a plurality of different predetermined sizes to accommodate a plurality of blocks of texture data having different sizes.

3. The method of claim 2, further comprising:

swapping the plurality of blocks between the high latency memory and the low latency memory via the plurality of transfer spaces, wherein blocks having substantially the same predetermined sizes are transferred via corresponding transfer spaces having substantially the same predetermined sizes.

4. The method of claim 2, wherein each of said plurality of transfer spaces corresponds to each of a plurality of predetermined sizes.

5. The method of claim 1, wherein the transfers of texture data are free of calls to an operating system of the computer system.

6. The method of claim 1, wherein the transfers texture data are configured to avoid fragmentation of the low latency memory.

7. The method of claim 1, further comprising:

sorting a plurality of blocks of texture data in the high latency memory and the low latency memory into a plurality of groups, wherein each of the groups has a different predetermined size corresponding to a size of a respective texture of each group.

8. The method of claim 7, further comprising:

implementing the transfers of the blocks of texture data between the high latency memory and the low latency memory within each of the groups, wherein transfers within each group execute independently.

9. The method of claim 1, wherein the copying is performed by a graphics driver process executing a DMA transfer.

10. A computer system for accessing texture data, comprising:

a graphics processor; and

a memory coupled to the graphics processor and having computer readable code which when executed by the graphics processor cause the graphics processor to perform a method for implementing transfers of texture data, comprising;

accessing a first block of texture data in a low latency memory, the first block having a predetermined size corresponding to a size of a texture stored in said first block of texture data;

accessing a second block of texture data in high latency memory, the second block having the predetermined size;

copying the first block of texture data from the low latency memory to a transfer space in high latency memory having the predetermined size, wherein the transfer space is allocated to accommodate a block of texture data of the predetermined size, wherein said transfer space is in a location separate from said first block of texture data and said second block of texture data;

writing the second block of texture data from the high latency memory to the low latency memory, wherein the second block overwrites the first block; and

accessing what used to be the transfer space as the first block in high latency memory, wherein what used to be the second block is accessed as a new transfer space.

11. The system of claim 10, wherein a plurality of transfer spaces are configured with a plurality of different predetermined sizes to accommodate a plurality of blocks of texture data having different sizes.

12. The system of claim 11, further comprising:

swapping the plurality of blocks between the high latency memory and the low latency memory via the plurality of transfer spaces, wherein blocks having substantially the same predetermined sizes are transferred via corresponding transfer spaces having substantially the same predetermined sizes.

13. The system of claim 10, wherein the transfers of texture data are free of calls to an operating system of the computer system.

14. The system of claim 10, wherein the transfers texture data are configured to avoid fragmentation of the low latency memory.

15. The system of claim 10, further comprising:

sorting a plurality of blocks of texture data in the high latency memory and the low latency memory into a plurality of groups, wherein each of the groups has a different p redetermined size corresponding to a size of a respective texture of each group.

16. The system of claim 10, further comprising:

implementing the transfers of the blocks of texture data between the high latency memory and the low latency memory within each of the groups, wherein transfers within each group execute independently.

17. A non-transitory computer readable media having computer readable code which when executed by a graphics processor of a computer system cause the computer system to perform a method for implementing transfers of texture data in the computer system, comprising:

accessing a first block of texture data in a low latency memory, the first block having a predetermined size corresponding to a size of a texture stored in said first block of texture data;

accessing a second block of texture data in high latency memory, the second block having the predetermined size;

copying the first block of texture data from the low latency memory to a transfer space in high latency memory having the predetermined size, wherein the transfer space is allocated to accommodate a texture block of the predetermined size, wherein said transfer space is in a location separate from said first block of texture data and said second block of texture data;

writing the second block of texture data from the high latency memory to the low latency memory, wherein the second block overwrites the first block; and

accessing what used to be the transfer space as the first block in high latency memory, wherein what used to be the second block is accessed as a new transfer space.

18. The non-transitory computer readable media of claim 17, wherein a plurality of transfer spaces are configured with a plurality of different predetermined sizes to accommodate a plurality of blocks of texture data having different sizes.

19. The non-transitory computer readable media of claim 18, further comprising:

swapping the plurality of blocks between the high latency memory and the low latency memory via the plurality of transfer spaces, wherein blocks having substantially the same predetermined sizes are transferred via corresponding transfer spaces having substantially the same predetermined sizes.

20. The non-transitory computer readable media of claim 18, wherein the blocks are transferred from the low latency memory on a least recently used basis.

21. The non-transitory computer readable media of claim 20, wherein each of the blocks of the predetermined size in the low latency memory are linked via a first plurality of pointers, and wherein each of the blocks of the predetermined size in the high latency memory are linked via a second plurality of pointers.

22. The non-transitory computer readable media of claim 17, wherein the transfers of texture data are free of calls to an operating system of the computer system.