Push-pull memory cell configured for simultaneous programming of n-channel and p-channel non-volatile transistors

• US 7,929,345 B2
• Filed: 12/23/2008
• Issued: 04/19/2011
• Est. Priority Date: 12/23/2008
• Status: Expired due to Fees

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Issaq, A. Farid
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Norman, James G
• Application Number:
  US12/343,308
• Publication Number:
  US 20100157688A1
• Time in Patent Office: 847 Days
• Field of Search: None
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates

Abstract

A method of for programming a push-pull memory cell to simultaneously program a p-channel non-volatile transistor and an n-channel non-volatile transistor includes driving to 0v wordlines for any row in which programming of memory cells is to be inhibited; driving to a positive voltage wordlines any row in which programming of memory cells is to be performed; driving to a positive voltage the bitlines for any column in which programming of memory cells is to be inhibited; driving to a negative voltage the bitlines for any column in which programming of memory cells is to be performed; driving to one of 0v and a negative voltage a center wordline for any row in which programming of memory cells is to be inhibited; and driving to one of 0v and a positive voltage the center wordline for any row in which programming of memory cells is to be performed.

Claims

1. In an array of push-pull memory cells arranged in a plurality of rows and columns, the array comprising a V_p line associated with each row of the array, a p-wordline associated with each row of the array, an n-wordline associated with each row of the array, a program wordline associated with each row of the array, a bit line associated with each column of the array, and a plurality of memory cells, each memory cell uniquely associated with a row in the array and a column in the array, each memory cell including a p-channel non-volatile transistor having a source coupled to the Vp line associated with its row, a drain, a floating gate and a control gate, the control gate coupled to the p-wordline associated with its row, a p-channel volatile transistor having a source coupled to the drain of the p-channel non-volatile transistor, a drain, and a control gate and a floating gate shorted together and coupled to the program wordline associated with its row, and an n-channel non-volatile transistor having a source coupled to the bit line associated with its column, a drain coupled to the drain of the p-channel volatile transistor, a floating gate and a control gate, the control gate coupled to an n-word line associated with its row, a method for simultaneously programming the n-channel and p-channel non-volatile transistors in a selected memory cell comprising:

driving to 0 v the p-wordline and the n-wordline for any row in which programming of memory cells is to be inhibited;

driving to a positive voltage the p-wordline and the n-wordline for any row in which programming of memory cells is to be performed;

driving to a positive voltage the bit line for any column in which programming of memory cells is to be inhibited;

driving to a negative voltage the bit line for any column in which programming of memory cells is to be performed;

driving to one of 0 v and a negative voltage the program wordline for any row in which programming of memory cells is to be inhibited; and

driving to one of 0 v and a positive voltage the program wordline for any row in which programming of memory cells is to be performed.

2. The method of claim 1 wherein driving to one of 0 v and a negative the program wordline for any row in which programming of memory cells is to be inhibited comprises driving the program wordline for any row in which programming of memory cells is to be inhibited to 0 v .

3. The method of claim 1 wherein driving to one of 0 v and a negative voltage the program wordline for any row in which programming of memory cells is to be inhibited comprises driving the program wordline for any row in which programming of memory cells is to be inhibited to a negative voltage.

4. The method of claim 1 wherein driving to one of 0 v and a positive voltage the program wordline for any row in which programming of memory cells is to be performed comprises driving the program wordline for any row in which programming of memory cells is to be performed to 0 v.

5. The method of claim 1 wherein driving to one of 0 v and a positive voltage the program wordline for any row in which programming of memory cells is to be performed comprises driving the program wordline for any row in which programming of memory cells is to be performed to a positive voltage.

6. The method of claim 1 wherein each p-channel non-volatile transistor and each p-channel non-volatile transistor are formed in a deep n-well, the method further including biasing the deep n-well at a positive voltage.

7. The method of claim 1 wherein each n-channel non-volatile transistor is formed in a high-voltage p-well disposed in the deep n-well, the method further including biasing the deep n-well at a negative voltage.

8. The method of claim 1 wherein driving to a positive voltage the program wordline for any row in which programming of memory cells is to be performed comprises driving the program wordline to a first positive voltage and further including driving the n-wordline to a second positive voltage less than the first positive voltage.

9. In an array of push-pull memory cells arranged in a plurality of rows and columns and comprising a p-word line associated with each row of the array, an n-word line associated with each row of the array, a program-word line associated with each row of the array, a p-bit line associated with each column of the array, an n-bit line associated with each column of the array, a plurality of memory cells, each memory cell uniquely associated with a row in the array and a column in the array, each memory cell including a p-channel non-volatile transistor having a source coupled to the p-bit line associated with its column, a drain, a floating gate and a control gate, the control gate coupled to the p-word line associated with its row, a p-channel volatile transistor having a source coupled to the drain of the p-channel non-volatile transistor, a drain, and a control gate and a floating gate shorted together and coupled to the program-word line associated with its row, and an n-channel non-volatile transistor having a source coupled to the n-bit line associated with its column, a drain coupled to the drain of the p-channel volatile transistor, a floating gate and a control gate, the control gate coupled to the n-word line associated with its row, a method for simultaneously programming the n-channel and p-channel non-volatile transistors in a selected memory cell comprising:

driving to 0 v the p-word line and the n-word line for any row in which programming of memory cells is to be inhibited;

driving to a negative voltage the program wordline for any row in which programming of memory cells is to be inhibited;

driving to a positive voltage the p-word line and the n-word line in any row in which programming of memory cells is to be performed;

driving to 0 v the p-bitline for any column in which programming of memory cells is to be inhibited;

driving to a positive voltage the n-bitline for any column in which programming of memory cells is to be inhibited;

driving to 0 v the p-bitline for any column in which programming of memory cells is to be performed;

driving to a negative voltage the n-bitline for any column in which programming of memory cells is to be performed;

driving to a first negative voltage program wordline for any row in which programming of memory cells is to be inhibited; and

driving to a second negative voltage more negative than the first negative voltage program wordline for any row in which programming of memory cells is to be performed.

10. The method of claim 9 wherein each p-channel non-volatile transistor and each p-channel non-volatile transistor are formed in a deep n-well, the method further including biasing the deep n-well at a positive voltage.

11. The method of claim 9 wherein each n-channel non-volatile transistor is formed in a high-voltage p-well disposed in the deep n-well, the method further including biasing the deep n-well at a negative voltage.

12. The method of claim 9 wherein driving to a positive voltage the p-word line and the n-word line for any row in which programming of memory cells is to be performed comprises driving the p-wordline to a first positive voltage and further including driving the n-wordline to a second positive voltage less than the first positive voltage.