Systems and methods for a PLL-adjusted reference clock

• US 7,929,919 B2
• Filed: 09/25/2008
• Issued: 04/19/2011
• Est. Priority Date: 05/15/2008
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Coppin, Justin
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): Gannon; Levi
• Application Number:
  US12/237,869
• Publication Number:
  US 20100074388A1
• Time in Patent Office: 936 Days
• Field of Search: 331/172, 375/371, 375/376, 455/76, 455/260
• US Class Current: 455/76
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A system is provided, the system includes a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal. The system also includes a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal. The system also includes a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input. The PLL-adjusted reference clock is used to generate at least one other communication link clock signal.

Claims

1. A system, comprising:

a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal;

a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal; and

a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input,

wherein the PLL-adjusted reference clock is used to generate at least one other communication link clock signal.

2. The system of claim 1 wherein the PLL and the TX/RX module are components of a serial communication link.

3. The system of claim 2 wherein the divider is a component of the serial communication link.

4. The system of claim 2 wherein the serial communication link comprises a root complex.

5. The system of claim 1 wherein the TX/RX module and the communication link clock signal are compatible with PCI Express.

6. The system of claim 1 further comprising at least one serial communication link that receives the PLL-adjusted reference clock and generates a corresponding communication link clock signal.

7. An electronic device, comprising:

first and second communication links configured to exchange data; and

a reference clock generator that outputs a reference clock to the first communication link, wherein the first communication link multiplies the reference clock for use as a communication link clock signal and wherein the first communication link divides the communication link clock signal to generate a jitter-matched reference clock for use by the second communication link.

8. The electronic device of claim 7 further comprising a printed circuit board (PCB) upon which the first and second communication links are mounted.

9. The electronic device of claim 8 wherein the jitter-matched reference clock enables a PCB spacing between the first and second communication links to be greater than a predetermined spacing budget for communication links.

10. The electronic device of claim 8 wherein the jitter-matched reference clock enables a PCB trace performance between the first and second communication links to be less than a predetermined trace performance budget for communication links.

11. The electronic device of claim 7 wherein the first and second communication links comprise Peripheral Communication Interface (PCI) Express links.

12. A method performed by a first communication link, comprising:

receiving a first reference clock;

generating a first communication link clock signal by multiplying the first reference clock;

generating a second reference clock based on the communication link clock signal, the second reference clock follows a jitter pattern of the first communication link clock signal; and

providing the second reference clock to a second communication link to generate a second communication link clock signal for the second communication link.

13. The method of claim 12 wherein generating the second reference clock comprises dividing the communication link clock signal by a factor that enables the second reference clock to approximate a frequency of the first reference clock.

14. The method of claim 12 further comprising generating the second communication link clock signal based on the second reference clock.

15. The method of claim 14 further comprising exchanging data between communication links based on the first and second communication link clock signals.