Accelerating hardware co-simulation using dynamic replay on first-in-first-out-driven command processor

• US 7,930,162 B1
• Filed: 05/05/2008
• Issued: 04/19/2011
• Est. Priority Date: 05/05/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Seng, Shay Ping, Ou, Jingzhao, Chan, Chi Bun
• Primary Examiner(s): Jacob; Mary C
• Application Number:
  US12/115,340
• Time in Patent Office: 1,079 Days
• Field of Search: 703/14
• US Class Current: 703/14
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

An integrated circuit configured for hardware co-simulation can include a command processor, a replay buffer storing a command template, wherein the command template specifies an incomplete command, and a command first-in-first out (FIFO) memory storing complementary data for completion of the command template. The integrated circuit further can include a multiplexer coupled to the command processor, the replay buffer, and the command FIFO. The multiplexer, under control of the command processor, can selectively provide data from the replay buffer or the command FIFO to the command processor. The command processor, responsive to a replay command read during a hardware co-simulation session, can enter a replay mode, obtain the command template from the replay buffer, obtain the complementary data from the FIFO memory according to a symbol read from the command template, and form a complete command by joining the command template with the complementary data.

Claims

1. An integrated circuit configured for hardware co-simulation comprising:

a command processor;

a replay buffer coupled to the command processor and storing at least one command template, wherein each command template specifies an incomplete command;

a command first-in-first out (FIFO) memory storing complementary data for completion of the command template; and

a multiplexer coupled to the command processor, the replay buffer, and the command FIFO, wherein the multiplexer, under control of the command processor, selectively provides data from the replay buffer or the command FIFO to the command processor,

wherein the command processor, responsive to a replay command read during a hardware co-simulation session, enters a replay mode, obtains the command template from the replay buffer, obtains the complementary data from the FIFO memory according to a symbol read from the command template, and forms a complete command by joining the command template with the complementary data.

2. The integrated circuit of claim 1, wherein the replay buffer is a random access memory.

3. The integrated circuit of claim 1, wherein the command processor advances a read memory address of the replay buffer after reading a command template from the replay buffer.

4. The integrated circuit of claim 1, wherein the command processor, responsive to reading a jump command within the replay buffer, sets a read memory address of the replay buffer to a memory address specified by the jump command.

5. The integrated circuit of claim 1, wherein, responsive to receiving a program command from a host system during the hardware co-simulation session, the command processor stores at least one command template specified by the program command beginning at a memory address of the replay buffer that is specified by the program command.

6. The integrated circuit of claim 1, wherein the command processor identifies the symbol according to a parity bit and retrieves a number of data items specified by the symbol from the command FIFO memory.

7. The integrated circuit of claim 1, wherein the command processor, responsive to determining that the symbol specifies that no data is to be obtained from the command FIFO, exits replay mode and enters normal mode, wherein a next command to be read during hardware co-simulation is read from the command FIFO.

8. The integrated circuit of claim 1, wherein the command processor receives out-of-band signals, wherein the command processor, responsive to receiving an out-of-band signal, enters normal mode, wherein a next command to be read during hardware co-simulation is read from the command FIFO.

9. A method of performing hardware co-simulation using an integrated circuit and a host data processing system (host), comprising:

identifying recurring data that is to be sent from the host to the integrated circuit;

programming a replay buffer within the integrated circuit with at least one command template generated from the recurring data, wherein each command template is an incomplete command;

starting the hardware co-simulation session;

responsive to detecting a replay command from the host, reading the command template from the replay buffer and at least one data item from a command first-in-first-out (FIFO) memory;

forming a complete command by joining the command template and the data item; and

outputting the complete command.

10. The method of claim 9, wherein identifying recurring data comprises identifying at least one of an op-code or an operand that is to be sent from the host to the device under test (DUT) more than one time during the hardware co-simulation session.

11. The method of claim 9, further comprising loading at least one new command template into the replay buffer during the hardware co-simulation session.

12. The method of claim 11, wherein loading at least one new command template comprises:

receiving a program command from the host during the hardware co-simulation session; and

storing a command template specified by the program command beginning at a memory address of the replay buffer that is specified by the program command.

13. The method of claim 9, wherein reading the command template from the replay buffer and at least one data item from a command FIFO memory comprises:

identifying a symbol within the command template according to a parity bit; and

retrieving a number of data items from the command FIFO as specified by the symbol.

14. The method of claim 9, wherein reading the command template from the replay buffer and at least one data item from a command FIFO memory comprises:

identifying a symbol within the command template according to a parity bit;

determining that the symbol specifies a value of zero; and

responsive to determining that the symbol specifies a value of zero, exiting replay mode and entering normal mode, wherein a next command to be executed is read from the command FIFO.

15. A non-transitory computer-readable medium comprising computer-usable program code that, when loaded into an integrated circuit, configures the integrated circuit to implement a method of performing hardware co-simulation, the method comprising:

Instantiating a command processor;

Instantiating a replay buffer storing at least one command template, wherein each command template specifies an incomplete command;

Instantiating a command first-in-first out (FIFO) memory storing complementary data for completion of the command template; and

Instantiating a multiplexer coupled to the command processor, the replay buffer, and the command FIFO, wherein the multiplexer, under control of the command processor, selectively provides data from the replay buffer or the command FIFO to the command processor,

wherein the command processor, responsive to a replay command read during a hardware co-simulation session, enters a replay mode, obtains the command template from the replay buffer, obtains the complementary data from the FIFO memory according to a symbol read from the command template, and forms a complete command by joining the command template with the complementary data.

16. The non-transitory computer-readable medium of claim 15, wherein, responsive to receiving a program command from a host system during the hardware co-simulation session, the command processor stores at least one command template specified by the program command beginning at a memory address of the replay buffer that is specified by the program command.

17. The non-transitory computer-readable medium of claim 15, wherein the command processor identifies the symbol according to a parity bit and retrieves a number of data items specified by the symbol from the command FIFO memory.

18. The non-transitory computer-readable medium of claim 15, wherein the command processor, responsive to determining that the symbol specifies that no data is to be obtained from the command FIFO, enters normal mode, wherein a next command to be read during hardware co-simulation is read from the command FIFO.

19. The non-transitory computer-readable medium of claim 15, wherein the command processor receives out-of-band signals, wherein the command processor, responsive to receiving an out-of-band signal, enters normal mode, wherein a next command to be read during hardware co-simulation is read from the command FIFO.

20. The non-transitory computer-readable medium of claim 15, wherein the command processor, responsive to reading a jump command within the replay buffer, sets a read memory address of the replay buffer to a memory address specified by the jump command.