System to provide memory system power reduction without reducing overall memory system performance

• US 7,930,469 B2
• Filed: 01/24/2008
• Issued: 04/19/2011
• Est. Priority Date: 01/24/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E., Brittain, Mark A.
• Primary Examiner(s): Verbrugge; Kevin
• Application Number:
  US12/018,952
• Publication Number:
  US 20090190429A1
• Time in Patent Office: 1,181 Days
• Field of Search: None
• US Class Current: 711/105
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system is provided that provides memory system power reduction without reducing overall memory system performance. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth while the second operating frequency is independently decreased to reduce power being consumed by the set of memory devices.

Claims

1. A memory system, comprising:

a memory hub device integrated in a memory module;

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller reads the memory access command for the set of memory devices from the command queue at a second operating frequency, wherein receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency implements a fully asynchronous boundary within the memory hub device, wherein, using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth at the first operating frequency, and wherein the second operating frequency is independently decreased in order to reduce power being consumed by the set of memory devices.

2. The memory system of claim 1, wherein the first operating frequency is independent of the second operating frequency and wherein the first operating frequency is a frequency other than a multiple of the second operating frequency.

3. The memory system of claim 1, wherein the memory hub device further comprises a write data queue that receives memory write data from the external memory controller via the memory channel at the first operating frequency, wherein the memory hub controller reads the memory write data from the write data queue at the second operating frequency, and wherein receiving the write data at the first operating frequency and reading the write data at the second operating frequency implements the asynchronous boundary within the memory hub device of the memory module.

4. The memory system of claim 1, wherein the memory hub device further comprises a read data queue that transmits memory read data from the external memory controller via the memory channel at the first operating frequency, wherein the memory hub controller writes the read data to the read data queue at the second operating frequency, and wherein transmitting the read data at the first operating frequency and writing the read data at the second operating frequency implements the asynchronous boundary within the memory hub device of the memory module.

5. The memory system of claim 1, wherein the memory hub device further comprises:

a memory device data interface, coupled to a read data queue, a write data queue, and the set of memory devices, that provides a communication path between the set of memory devices and the read data queue or the write data queue.

6. The memory system of claim 5, wherein the memory hub controller controls the transfer of data between the write data queue and the set of memory devices and the transfer of data between the set of memory devices and the read data queue.

7. The memory system of claim 1, wherein the memory hub device further comprises:

a link interface, coupled to a memory device data interface, that provides a communication path between the memory module and the external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface.

8. The memory system of claim 1, wherein the memory hub device further comprises:

a link interface, coupled to the memory hub controller, that provides a communication path between the memory module and the external memory controller, and wherein the memory hub controller controls the transfer of the memory access command from the link interface to the set of memory devices.

9. The memory system of claim 8, wherein the memory hub controller further comprises:

a memory device sequencer that determines a proper clock cycle to issue the memory access command to the set of memory devices.

10. The memory system of claim 9, wherein the proper clock cycle is determined based on at least one of the specification of the set of memory devices or previous memory access commands sent to the set of memory devices.

11. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

12. The memory system of claim 1, wherein the memory module is part of a data processing device.

13. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising;

a memory hub device integrated in the memory module;

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller reads the memory access command for the set of memory devices from the command queue at a second operating frequency, wherein receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency implements an asynchronous boundary within the memory hub device of the memory module, wherein, using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth at the first operating frequency, and wherein the second operating frequency is independently decreased in order to reduce power being consumed by the set of memory devices.

14. The data processing system of claim 13, wherein the first operating frequency is independent of the second operating frequency and wherein the first operating frequency is a frequency other than a multiple of the second operating frequency.

15. The data processing system of claim 13, wherein the memory hub device further comprises a write data queue that receives memory write data from the external memory controller via the memory channel at the first operating frequency, wherein the memory hub controller reads the memory write data from the write data queue at the second operating frequency, and wherein receiving the write data at the first operating frequency and reading the write data at the second operating frequency implements the fully asynchronous boundary within the memory hub device.

16. The data processing system of claim 13, wherein the memory hub device further comprises a read data queue that transmits memory read data from the external memory controller via the memory channel at the first operating frequency, wherein the memory hub controller writes the read data to the read data queue at the second operating frequency, and wherein transmitting the read data at the first operating frequency and writing the read data at the second operating frequency implements the fully asynchronous boundary within the memory hub device.

17. The data processing system of claim 13, wherein the memory hub device further comprises:

a memory device data interface, coupled to a read data queue, a write data queue, and the set of memory devices, that provides a communication path between the set of memory devices and the read data queue or the write data queue.

18. The data processing system of claim 13, wherein the memory hub device further comprises:

a link interface, coupled to a memory device data interface, that provides a communication path between the memory module and the external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface.

19. The data processing system of claim 13, wherein the memory hub device further comprises:

a link interface, coupled to the memory hub controller, that provides a communication path between the memory module and the external memory controller, and wherein the memory hub controller controls the transfer of the memory access command from the link interface to the set of memory devices.

20. A method for implementing an asynchronous boundary in a memory module, comprising:

receiving, in a command queue of a memory hub device integrated in the memory module, a memory access command from an external memory controller via a memory channel at a first operating frequency; and

reading, by a memory hub controller integrated in the memory hub device, the memory access command for the set of memory devices from the command queue at a second operating frequency, wherein receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency implements the asynchronous boundary within the memory hub device of the memory module, wherein, using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth at the first operating frequency, and wherein the second operating frequency is independently decreased in order to reduce power being consumed by the set of memory devices.