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System to provide memory system power reduction without reducing overall memory system performance

  • US 7,930,469 B2
  • Filed: 01/24/2008
  • Issued: 04/19/2011
  • Est. Priority Date: 01/24/2008
  • Status: Expired due to Fees
First Claim
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1. A memory system, comprising:

  • a memory hub device integrated in a memory module;

    a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency; and

    a memory hub controller integrated in the memory hub device, wherein the memory hub controller reads the memory access command for the set of memory devices from the command queue at a second operating frequency, wherein receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency implements a fully asynchronous boundary within the memory hub device, wherein, using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth at the first operating frequency, and wherein the second operating frequency is independently decreased in order to reduce power being consumed by the set of memory devices.

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