Software model for a hybrid stacked field programmable gate array

• US 7,930,661 B1
• Filed: 08/04/2008
• Issued: 04/19/2011
• Est. Priority Date: 08/04/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M., New, Bernard J., Rahman, Arifur
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Parihar; Suchin
• Application Number:
  US12/185,511
• Time in Patent Office: 988 Days
• Field of Search: 716/1, 716/4, 716/100, 716/104
• US Class Current: 716/104
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software model of the first integrated circuit die includes an integrated circuit resource (614) and an internal interface (150). A software model of the second integrated circuit die includes a stacked resource (618). The software model of the internal interface is configurable to connect the stacked resource of the second integrated circuit die to the integrated circuit resource through the interchip communication interface.

Claims

1. A non-transitory computer-readable storage medium configured with software for generating a software model for characterizing a stacked integrated circuit system having a first integrated circuit die and a second integrated circuit die connected to the first integrated circuit die with an interchip communication interface, the software, when executed by a computer, causing the computer to perform steps comprising:

developing a software model of the first integrated circuit die including an first integrated circuit resource and an internal interface; and

developing a software model of the second integrated circuit die including a stacked resource, the software model of the internal interface being configurable to connect the stacked resource of the second integrated circuit die to the first integrated circuit resource through the interchip communication interface;

wherein the stacked resource is connected through an interconnection tile of the first integrated circuit die, and the interconnection tile includes a programmable heterogeneous integration (“

PHI”

) tile.

2. The non-transitory computer-readable storage medium of claim 1 wherein the interconnection tile and the interchip communication interface is in a center portion of the first integrated circuit die.

3. The non-transitory computer-readable storage medium of claim 1 wherein the interchip communication interface is in a logic portion of the first integrated circuit die.

4. The non-transitory computer-readable storage medium of claim 1 wherein the interchip communication interface is modeled as wiring of the first integrated circuit die.

5. The non-transitory computer-readable storage medium of claim 1 wherein the software model models the interchip communication interface as an internal interface communication bus of the first integrated circuit die.

6. The non-transitory computer-readable storage medium of claim 1 wherein the stacked resource is connected to fabric of the first integrated circuit die as a physical resource of the first integrated circuit die.

7. The non-transitory computer-readable storage medium of claim 1 wherein the stacked resource is a type of resource not found on the first integrated circuit die.

8. The non-transitory computer-readable storage medium of claim 1 wherein the stacked resource is a dynamic random access memory (“

DRAM”

) resource.

9. The non-transitory computer-readable storage medium of claim 8 wherein the software model of the first integrated circuit die includes a DRAM controller configured in the first integrated circuit die.

10. A method of modeling an integrated circuit system comprising:

on a computer, performing steps including;

developing a software model of a first integrated circuit die having an internal interface tile connectable to an interchip communication interface between the first integrated circuit die and a second integrated circuit die;

developing a software model of the second integrated circuit die including a stacked resource;

wherein the stacked resource is connected through an interconnection tile of the first integrated circuit die, and the interconnection tile includes a programmable heterogeneous integration (“

PHI”

) tile;

combining the software model of the second integrated circuit die with the software model of the first integrated circuit die to produce a software model of the integrated circuit system; and

emulating operation of the integrated circuit system by configuring the software model of the integrated circuit system according to an application so as to access the stacked resource through the internal interface tile.

11. The method of claim 10 wherein the software model of the first integrated circuit die includes an element library having configurable elements and second integrated circuit die elements.

12. The method of claim 11 wherein the element library further includes third integrated circuit die elements of a third integrated circuit die alternatively connectable to the first integrated circuit die through the interchip communication interface.

13. The method of claim 10 wherein the stacked resource is a type of resource not found on the first integrated circuit die.

14. The method of claim 13 wherein the stacked resource is a dynamic random access memory (“

DRAM”

) and the step of emulating includes configuring a DRAM controller in the first integrated circuit die.

15. The method of claim 10 further comprising producing a bit stream to configure the integrated circuit system according to the application.