Software model for a hybrid stacked field programmable gate array
First Claim
1. A non-transitory computer-readable storage medium configured with software for generating a software model for characterizing a stacked integrated circuit system having a first integrated circuit die and a second integrated circuit die connected to the first integrated circuit die with an interchip communication interface, the software, when executed by a computer, causing the computer to perform steps comprising:
- developing a software model of the first integrated circuit die including an first integrated circuit resource and an internal interface; and
developing a software model of the second integrated circuit die including a stacked resource, the software model of the internal interface being configurable to connect the stacked resource of the second integrated circuit die to the first integrated circuit resource through the interchip communication interface;
wherein the stacked resource is connected through an interconnection tile of the first integrated circuit die, and the interconnection tile includes a programmable heterogeneous integration (“
PHI”
) tile.
1 Assignment
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Accused Products
Abstract
A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software model of the first integrated circuit die includes an integrated circuit resource (614) and an internal interface (150). A software model of the second integrated circuit die includes a stacked resource (618). The software model of the internal interface is configurable to connect the stacked resource of the second integrated circuit die to the integrated circuit resource through the interchip communication interface.
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Citations
15 Claims
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1. A non-transitory computer-readable storage medium configured with software for generating a software model for characterizing a stacked integrated circuit system having a first integrated circuit die and a second integrated circuit die connected to the first integrated circuit die with an interchip communication interface, the software, when executed by a computer, causing the computer to perform steps comprising:
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developing a software model of the first integrated circuit die including an first integrated circuit resource and an internal interface; and developing a software model of the second integrated circuit die including a stacked resource, the software model of the internal interface being configurable to connect the stacked resource of the second integrated circuit die to the first integrated circuit resource through the interchip communication interface; wherein the stacked resource is connected through an interconnection tile of the first integrated circuit die, and the interconnection tile includes a programmable heterogeneous integration (“
PHI”
) tile. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of modeling an integrated circuit system comprising:
on a computer, performing steps including; developing a software model of a first integrated circuit die having an internal interface tile connectable to an interchip communication interface between the first integrated circuit die and a second integrated circuit die; developing a software model of the second integrated circuit die including a stacked resource; wherein the stacked resource is connected through an interconnection tile of the first integrated circuit die, and the interconnection tile includes a programmable heterogeneous integration (“
PHI”
) tile;combining the software model of the second integrated circuit die with the software model of the first integrated circuit die to produce a software model of the integrated circuit system; and emulating operation of the integrated circuit system by configuring the software model of the integrated circuit system according to an application so as to access the stacked resource through the internal interface tile. - View Dependent Claims (11, 12, 13, 14, 15)
Specification