System and method of providing a memory hierarchy

• US 7,930,666 B1
• Filed: 12/12/2006
• Issued: 04/19/2011
• Est. Priority Date: 12/12/2006
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Pugh, Daniel J., Teig, Steven
• Primary Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US11/609,875
• Time in Patent Office: 1,589 Days
• Field of Search: 716 3- 6, 716/16, 716/18, 703/14, 703/15, 326/38
• US Class Current: 716/115
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.

Claims

1. A computer-implemented method of implementing a user integrated circuit (IC) design in a physical IC that has a memory comprising a single physical port, said method comprising:

mapping memory accesses in the user design to the memory by using a plurality of logical ports for the memory that has a particular port hierarchy with at least a first logical port that has a higher priority in the particular port hierarchy than a second logical port with a lower priority, wherein the plurality of logical ports for the memory are emulated in a user design clock cycle by accessing the single physical port of the memory a plurality of times in the user design clock cycle; and

resolving conflicts resulting from mapping a first memory access and a second memory access in the user design to a particular user design clock cycle by assigning the first memory access to the higher-priority first logical port of the memory while assigning the second memory access to the lower-priority second logical port of the memory, said assignments of the first and second memory accesses setting the first memory access to occur prior to the second memory access, wherein said mapping and resolving are performed by a design automation tool implemented on a computer.

2. The computer-implemented method of claim 1, wherein said first and second logical ports each access a same memory address.

3. The computer-implemented method of claim 2, wherein said accesses of the same memory address by said first and second logical ports comprise:

said second logical port writing a first memory value to said same memory address; and

said first logical port reading a second memory value from said same memory address, wherein said second memory value is a memory value that was stored in said same memory address prior to said second logical port writing to said same memory address.

4. The computer-implemented method of claim 2, wherein said accesses of the same memory address by said first and second logical ports comprise:

said first logical port writing a first memory value to said same memory address; and

said second logical port reading a second memory value from said same memory address, wherein said second memory value is equal to said first memory value.

5. The computer-implemented method of claim 1, wherein said memory accesses are mapped to a plurality of sequential accesses to said single physical memory port within the particular user design clock cycle.

6. The computer-implemented method of claim 1, wherein said IC comprises a plurality of reconfigurable circuits that reconfigure once per subcycle of the user design clock cycle and said memory is accessed once per subcycle through said single physical port.

7. The computer-implemented method of claim 1, wherein the first memory access is an access to the single physical port in a first subcycle of the particular user design clock cycle while the second memory access is an access to the single physical port in a second subcycle of the particular user design clock cycle that is after the first subcycle.

8. A computer-implemented method of implementing a user integrated circuit (IC) design in an IC that has a memory comprising a plurality of physical ports, said method comprising:

mapping memory accesses in the user design to the memory by using a plurality of logical ports for the memory that has a particular port hierarchy with at least a first logical port that has a higher priority in the particular port hierarchy than a second logical port with a lower priority, wherein said plurality of logical ports for the memory are M logical ports that are emulated in a user design clock cycle by accessing N physical ports of the memory a plurality of times in the user design clock cycle, wherein M and N are integers greater than one and wherein M>

N, wherein at least one of the N physical ports is accessed more than once in the user design clock cycle in order to emulate accesses by two or more of the M logical ports; and

resolving conflicts resulting from mapping a first memory access and a second memory access in the user design to a particular user design clock cycle by assigning the first memory access to the higher-priority first logical port of the memory while assigning the second memory access to the lower-priority second logical port of the memory, said assignments of the first and second memory accesses setting the first memory access to occur prior to the second memory access, wherein said mapping and resolving are implemented on a computer.

9. The computer-implemented method of claim 8, wherein a plurality of times in emulating the logical ports further comprises accessing each of a plurality of said N physical ports the user design clock cycle.

10. A computer-implemented method of accessing memory in an integrated circuit (IC), said method comprising:

mapping memory accesses in a user design to a memory in the IC by using a plurality of ports for the memory, the plurality of ports having a particular port hierarchy with at least a first port that has a higher priority in the port hierarchy than a second port with a lower priority, wherein the plurality of ports for the memory are a plurality of logical ports that are emulated in a user design clock cycle by accessing a single physical port of the memory a plurality of times in the user design clock cycle; and

resolving conflicts resulting from mapping a first memory access in the user design to a particular user design clock cycle and a second memory access in the user design to the particular user design clock cycle by assigning the first memory access to the higher-priority first port of the memory while assigning the second memory access to the lower-priority second port of the memory, said assignments of the first and second memory accesses setting the first memory access to occur prior to the second memory access, wherein said mapping and resolving are implemented on a computer.

11. The computer-implemented method of claim 10, wherein said first and second memory ports each access a same memory address.

12. The computer-implemented method of claim 11, wherein said first and second memory accesses comprise:

said second memory port writing a first memory value to said same memory address; and

said first memory port reading a second memory value from said same memory address, wherein said second memory value is a memory value that was stored in said same memory address prior to said second memory port writing to said same memory address.

13. The computer-implemented method of claim 11, wherein said first and second memory accesses comprise:

said first memory port writing a first memory value to said same memory address; and

said second memory port reading a second memory value from said same memory address, wherein said second memory value is equal to said first memory value.

14. The computer-implemented method of claim 10, wherein said memory accesses are mapped to a plurality of sequential accesses to said single physical port within the user design clock cycle.

15. The computer-implemented method of claim 14, wherein said IC comprises a plurality of reconfigurable circuits that reconfigure once per subcycle of the user design clock cycle and said memory is accessed once per subcycle through said single physical port.

16. A computer-implemented method of accessing memory in an integrated circuit (IC), said method comprising:

mapping memory accesses in a user design to a memory in the IC by using a plurality of ports for the memory that have a particular port hierarchy with at least a first port that has a higher priority in the port hierarchy than a second port with a lower priority, wherein said plurality of ports for the memory are M logical ports that are emulated in a user design clock cycle by accessing N physical ports of the memory a plurality of times in the user design clock cycle, wherein M and N are integers greater than one and wherein M>

N, wherein accesses to two or more of the M logical ports are emulated by two or more accesses to one of the N physical ports in the user design clock cycle; and

resolving conflicts from mapping a first memory access in the user design to a particular user design clock cycle and a second memory access in the user design to the particular user design clock cycle by assigning the first memory access to the higher-priority first port of the memory while assigning the second memory access to the lower-priority second port of the memory, said assignments of the first and second memory accesses setting the first memory access to occur prior to the second memory access, wherein said mapping and resolving are implemented on a computer.

17. The computer-implemented method of claim 16, wherein the first memory access is an access to a particular physical port in a first subcycle, while the second memory access is an access to the particular physical port in a second subcycle that is after the first subcycle in the particular user design clock cycle.

18. The computer implemented method of claim 16, wherein emulating the M logical ports further comprises accessing each of a plurality of said N physical ports a plurality of times in the particular user design clock cycle.