Edge gas injection for critical dimension uniformity improvement

• US 7,932,181 B2
• Filed: 06/20/2006
• Issued: 04/26/2011
• Est. Priority Date: 06/20/2006
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Cooperberg, David, Vahedi, Vahid, Singh, Harmeet
• Primary Examiner(s): Tran; Binh X
• Assistant Examiner(s): Dahimene; Mahmoud
• Application Number:
  US11/455,671
• Publication Number:
  US 20070293043A1
• Time in Patent Office: 1,771 Days
• Field of Search: 438/689, 216/67, 216/68
• US Class Current: 438/689
• CPC Class Codes: H01J 2237/334 Etching
• CPC Class Codes: H01J 37/321 the radio frequency energy being inductively coupled to the plasma
• CPC Class Codes: H01J 37/3244 Gas supply means
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/6708 using mainly spraying means, e.g. nozzles

Abstract

A method of etching a semiconductor substrate with improved critical dimension uniformity comprises supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber; supplying a first etch gas to a central region over the semiconductor substrate; supplying a second gas comprising at least one silicon containing gas to a peripheral region over the semiconductor substrate surrounding the central region, wherein a concentration of silicon in the second gas is greater than a concentration of silicon in the first etch gas; generating plasma from the first etch gas and second gas; and plasma etching an exposed surface of the semiconductor substrate.

Claims

1. A method of etching a semiconductor substrate with improved critical dimension uniformity comprising:

supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber;

supplying a first etch gas comprising a silicon containing gas to a central region over the semiconductor substrate;

supplying a second gas comprising at least one silicon containing gas to a peripheral region over the semiconductor substrate surrounding the central region, wherein a concentration of silicon in the second gas is greater than a concentration of silicon in the first etch gas;

adjusting an amount of silicon in the first etch gas relative to an amount of silicon in the second gas;

generating a plasma from the first etch gas and second gas by inductively coupling radio frequency energy into the chamber; and

plasma etching an exposed surface of the semiconductor substrate with the plasma;

at least one passivating species comprising silicon passivates sidewalls of features etched into the semiconductor substrate; and

the first etch gas comprises chlorine and the passivating species comprising silicon comprises SiCl_x, wherein x is 1, 2, 3 or 4.

2. The method of claim 1, comprising plasma etching a feature selected from the group consisting of at least one opening, via, trench, and gate structure in the exposed surface of the semiconductor substrate.

3. The method of claim 1, wherein the passivating species comprising silicon results from the plasma etching and from the second gas.

4. The method of claim 1, wherein the passivating species comprising silicon is provided by the silicon containing gas.

5. The method of claim 1, wherein the silicon containing gas is selected from the group consisting of SiCl₄, SiHCl₃, SiH₂Cl₂, SiH₃Cl and mixtures thereof.

6. The method of claim 1, wherein the second gas further comprises an inert carrier gas.

7. The method of claim 6, wherein the inert carrier gas is selected from the group consisting of He, Ne, Ar, Kr, Xe, and mixtures thereof.

8. The method of claim 1, wherein the second gas further comprises an etchant gas.

9. The method of claim 8, wherein the etchant gas is selected from the group consisting of Cl₂, HBr, CF, CF₂, CF₃, CH₂F₂, SF₆, HCl, and mixtures thereof.

10. The method of claim 1, wherein the second gas further comprises a passivation gas.

11. The method of claim 10, wherein the passivation gas is selected from the group consisting of O₂, N₂, and mixtures thereof.

12. The method of claim 1, wherein plasma is generated by inductively coupling radio frequency energy into the plasma chamber by supplying radio frequency energy to a planar coil arranged parallel to the semiconductor substrate.

13. The method of claim 2, wherein a feature etched near a center of the semiconductor substrate is substantially uniform with an equivalent feature etched closer to an edge of the wafer.

14. The method of claim 13, wherein the semiconductor substrate is a 300 mm wafer and the features are less than 50 nm and have less than or equal to 1.5 nm 3σ

non-uniformity.

15. A method of etching a semiconductor substrate with improved critical dimension uniformity comprising:

supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber;

supplying a first etch gas comprising a silicon containing gas to a central region over the semiconductor substrate;

supplying a second gas comprising at least one silicon containing gas to a peripheral region over the semiconductor substrate surrounding the central region, wherein a concentration of silicon in the second gas is greater than a concentration of silicon in the first etch gas;

adjusting an amount of silicon in the first etch gas relative to an amount of silicon in the second gas;

generating a plasma from the first etch gas and second gas by inductively coupling radio frequency energy into the chamber; and

plasma etching an exposed surface of the semiconductor substrate with the plasma;

wherein the exposed surface of the semiconductor substrate comprises a silicon layer; and

the silicon layer comprises an exposed region of a single crystal silicon wafer, an exposed region of a strained silicon layer or a silicon germanium layer.

16. The method of claim 15, wherein the silicon layer is beneath a silicon nitride, silicon oxide, or silicon oxynitride, mask layer.

17. The method of claim 15, wherein the silicon layer is between an underlying gate oxide and an overlying hard or soft mask layer or photoresist.

18. The method of claim 17, wherein the silicon layer is beneath a silicon nitride, silicon oxide, or silicon oxynitride mask layer or photoresist.

19. A method of etching a semiconductor substrate with improved critical dimension uniformity comprising:

supporting a semiconductor substrate on a substrate support in an inductively coupled plasma etch chamber;

supplying a first etch gas comprising a silicon containing gas to a central region over the semiconductor substrate;

supplying a second gas comprising at least one silicon containing gas to a peripheral region over the semiconductor substrate surrounding the central region, wherein a concentration of silicon in the second gas is greater than a concentration of silicon in the first etch gas;

adjusting an amount of silicon in the first etch gas relative to an amount of silicon in the second gas;

generating a plasma from the first etch gas and second gas by inductively coupling radio frequency energy into the chamber; and

plasma etching an exposed surface of the semiconductor substrate with the plasma;

wherein the second gas comprises a mixture of (i) SiCl₄, (ii) C_xF_y or C_xF_yH_z and (iii) an inert gas.