Power rectifiers and method of making same

• US 7,932,536 B2
• Filed: 09/10/2008
• Issued: 04/26/2011
• Est. Priority Date: 03/09/2007
• Status: Active Grant

• Current Assignee: Diodes Incorporated
• Original Assignee: Diodes Incorporated
• Inventors: Eastman, Timothy S., Hamerski, Roman Jan, Moult, Jonathan
• Primary Examiner(s): NGUYEN, NIKI HOANG
• Assistant Examiner(s): Nguyen; Tram H
• Application Number:
  US12/208,215
• Publication Number:
  US 20090039384A1
• Time in Patent Office: 958 Days
• Field of Search: 438/270, 438/197, 438/268, 438/502, 438/509, 438660-664, 438/530, 438/540, 257/334, 257/E27.091, 257/E29.166, 257/E29.226, 257E29255-E29257, 257/214, 257/216, 257/302, 257/328, 257/331, 257/E21.262, 257/E21.41, 257/E29.012, 257/E29.013, 257/E27.052, 257/E27.079, 257E29036-E29038, 257E29046-E29048, 257/E29.115, 257/E29.196, 257E29211-E29225, 257/E21.077, 257/E21.082, 257/E21.333, 257/E21.12, 257/E21.324, 257/E21.454, 257/E21.497, 257/E33.075, 257/109, 257155-156
• US Class Current: 257/104
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/365 Planar doping, e.g. atomic-plane doping, delta-doping
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66151 Tunnel diodes group 13/15 resonant tunneling diodes H01L29/66219
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8618 Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H01L 29/88 Tunnel-effect diodes

Abstract

In one embodiment the present invention includes a semiconductor rectifier device comprising a first, second, and third semiconductor regions and a gate. The first semiconductor region is of a first conductivity type. The second semiconductor region is adjacent to the first semiconductor region which has a second conductivity type. The third semiconductor region is adjacent to the second semiconductor region which has the second conductivity type. The gate is proximate to but insulated from the second semiconductor region and electrically coupled to the third semiconductor region. When the first semiconductor region is biased in a first direction, an inversion region forms in the second semiconductor region. The inversion region forms a forward-biased tunnel diode junction with the third semiconductor region. When the first semiconductor region is biased a second direction, the semiconductor rectifier device functions as a reverse-biased PIN diode.

Claims

1. A method of manufacturing a semiconductor rectifier device, the method comprising:

depositing an N-drift region on an N++ substrate;

implanting boron into the N-drift region to create a P-body layer;

forming a plurality of trenches within the P-body layer, the trenches forming a plurality of P-body regions;

forming a dielectric layer within each trench of the plurality of trenches;

depositing conductive gate material to fill a remaining volume within each trench of the plurality of trenches;

etching back the conductive gate material to form a planar surface above the plurality of P-body regions;

depositing a layer of titanium and a layer of titanium nitride on the planar surface;

annealing to create a layer of titanium silicide at an interface between the plurality of P-body regions and the titanium layer, and in accordance therewith, forming a δ

p++ layer.

2. The method of claim 1 wherein the annealing has a peak temperature of 710 degrees Celsius and an annealing time from 15 seconds to 75 seconds.

3. The method of claim 1 wherein the annealing has an annealing time from 15 seconds to 75 seconds.

4. The method of claim 1 wherein the forming the dielectric layer includes growing a gate oxide between 20 Angstroms and 200 Angstroms.

5. The method of claim 1 wherein the conductive gate material is a polysilicon doped with phosphorous using a LPCVD system.

6. The method of claim 1 wherein the forming the plurality of trenches includes:

performing lithography to define the trenches; and

etching the trenches to a depth between 0.3 μ

m to 2.0 μ

m.

7. The method of claim 1 wherein depositing the N-drift region on the N++ substrate includes epitaxially depositing to create the N-drift region and

wherein the N++ substrate is an arsenic-doped or phosphorus-doped single crystal silicon substrate having a resistivity lower than 0.005 Ω

cm.

8. The method of claim 1 wherein the N-drift region has a resistivity of approximately 0.4 Ω

cm and a thickness of approximately 4 μ

m.

9. The method of claim 1 further comprising

growing a oxide within the trench prior to forming the dielectric layer;

etching the oxide which leaves a bottom of the trenches of the plurality of trenches free of silicon dioxide;

implanting boron at the bottom of the trenches of the plurality of trenches;

activating the boron at the bottom of the trenches of the plurality of trenches; and

removing the oxide.

10. The method of claim 9 wherein the activating the boron at the bottom of the trenches of the plurality of trenches includes using rapid thermal annealing at approximately 1000 degrees Celsius for a time between 15 to 60 seconds.

11. A semiconductor rectifier device comprising:

an anode terminal;

a δ

p++ layer electrically coupled to the anode terminal;

a P-body region located adjacent to the δ

p++ layer;

an N-drift region located adjacent to the P-body region;

an N++ substrate located adjacent to the N-drift region;

a cathode terminal electrically coupled to the N++ substrate;

a dielectric layer perpendicular to the δ

p++ layer and adjacent to the P-body region; and

a conductive layer adjacent and parallel to the dielectric layer, the conductive layer electrically coupled to the anode terminal,

wherein if a forward bias of the semiconductor rectifier device is provided across the anode and cathode terminals, the P-body region inverts and becomes an n-type conductive channel, and in accordance therewith, an interface of a portion of the δ

p++ layer and the n-type conductive channel form a tunnel diode.

12. The semiconductor rectifier device of claim 11 wherein the P-body region has a low doping concentration such that the P-body region may be inverted with the forward bias being near 0 volts, and in accordance therewith, improve the efficiency of the rectifier.

13. The semiconductor rectifier device of claim 11 wherein the δ

p++ layer does not have a width beyond several atomic layers such that the doping concentration of the layer does not have a significant length parallel along the dielectric and conductive layers, and in accordance therewith, the δ

p++ layer does not significantly inhibit the inversion of the P-body region when the forward bias is provided.

14. The semiconductor rectifier device of claim 11 wherein if a reverse bias of the semiconductor rectifier device is provided to the anode and cathode terminals, the P-body, N-drift region, and the N++ substrate form a PIN diode such that a reverse leakage current is reduced.

15. The semiconductor rectifier device of claim 11 further comprising a second P-body region adjacent to the δ

p++ layer,

wherein the dielectric layer and the conductive layer are formed within a trench and the P-body region is located adjacent to a first side of the trench and the second P-body region is located on a second side of the trench,

wherein the dielectric layer forms a first layer within the trench and the conductive layer fills in a remaining volume of the trench,

wherein the trench protrudes within the N-drift region,

wherein if the forward bias is provided to the anode and cathode terminals, the second P-body region inverts and becomes a second n-type conductive channel, and in accordance therewith, an interface of a second portion of the δ

p++ layer and the n-type conductive channel form a second tunnel diode.

16. The semiconductor rectifier device of claim 15 further comprising a P-implanted region at a bottom of the trench,

wherein the P-implanted region lies between the dielectric layer and the N-drift area, the conductive layer having corners at the bottom of the trench,

wherein the P-conductive area reduces high electric field intensity at the corners of the trench.

17. A semiconductor rectifier device comprising:

an anode terminal;

a δ

p++ layer electrically coupled to the anode terminal;

a plurality of P-body regions each located adjacent to a portion of the δ

p++ layer;

an N-drift region located adjacent to the plurality of P-body regions;

a plurality of trenches having sides adjacent to the P-body regions and having a bottom protruding within the n-drift region, each trench comprising,

a dielectric layer forming a first layer covering the sides and bottom of the trench,

a conductive layer filling a remaining volume within the trench;

an N++ substrate located adjacent to the N-drift region;

a cathode terminal electrically coupled to the N++ substrate;

wherein if a forward bias of the semiconductor rectifier device is provided across the anode and cathode terminals, each side of the P-body region of the plurality of P-body regions inverts and becomes an n-type conductive channel, and in accordance therewith, a plurality of interfaces between a plurality of portions of the δ

p++ layer and their corresponding n-type conductive channels form a plurality of tunnel diodes.

18. The semiconductor rectifier device of claim 17 wherein the plurality of P-body regions each have a low doping concentration such that each P-body region may be inverted with the forward bias being near 0 volts, and in accordance therewith, improve the efficiency of the rectifier.

19. The semiconductor rectifier device of claim 17 wherein the δ

p++ layer does not have a width beyond several atomic layers such that the doping concentration of the layer does not have a significant length parallel along the dielectric and conductive layers within the plurality of trenches, and in accordance therewith, the δ

p++ layer does not significantly inhibit the inversion of the plurality of P-body regions when the forward bias is provided.

20. The semiconductor rectifier device of claim 17 wherein if a reverse bias of the semiconductor rectifier device is provided to the anode and cathode terminals, the plurality of P-body, the N-drift region, and the N++ substrate form a PIN diode such that the reverse leakage current is reduced.