Systems and methods for fabricating self-aligned memory cell

• US 7,932,548 B2
• Filed: 07/14/2006
• Issued: 04/26/2011
• Est. Priority Date: 07/14/2006
• Status: Expired due to Fees

• Current Assignee: 4D-S Pty, Ltd.
• Original Assignee: 4D-S Pty, Ltd.
• Inventors: Nagashima, Makoto
• Primary Examiner(s): Le; Thao P.
• Application Number:
  US11/486,472
• Publication Number:
  US 20080014750A1
• Time in Patent Office: 1,747 Days
• Field of Search: 257/296
• US Class Current: 257/296
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr_1-XCa_XMnO₃ (PCMO) layer above the insulator and the metal portions, wherein X is between approximately 0.3 and approximately 0.5, to form one or more self-aligned RRAM cells above the first metal electrode; and depositing a second metal electrode layer above the PCMO layer.

Claims

1. A resistive random access memory (RRAM) comprising:

a. an insulator material deposited and patterned to expose metal openings; and

b. a PCMO layer deposited above the patterned insulator material forming one or more self-aligned RRAM cells without any etching of the PCMO layer wherein the PCMO layer is deposited above the insulator material to form an amorphous silicon material, and wherein the PCMO layer is deposited above the metal openings to form polycrystalline PCMO.

2. The RRAM of claim 1, comprising a plurality of metal layers and vias coupling the RRAM cells to a wafer circuit.

3. The RRAM of claim 2, comprising stacking a plurality of layers of polycrystalline PCMO to form a 3-dimensional RAM structure.