Stacked chip-based system and method

• US 7,932,584 B2
• Filed: 02/16/2007
• Issued: 04/26/2011
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): Warren; Matthew E
• Application Number:
  US11/675,756
• Publication Number:
  US 20070196948A1
• Time in Patent Office: 1,530 Days
• Field of Search: 257/621, 257/698, 257/777, 257/778, 257/E23.011, 257/E23.169, 257/E23.174, 257/E25.015
• US Class Current: 257/621
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0615 : Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/13012 : in top view
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8121 : using a reflow oven
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/427 : Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 428/24174 : including sheet or component perpendicular to plane of web or sheet

Abstract

A system has multiple discrete functional system subcomponents which, when interconnected form the system, each of the subcomponents being on a discrete substrate and being electrically interconnected to at least one of the other subcomponents by a through-chip via. A method of creating a system involves creating multiple discrete chips, each including at least one system subcomponent, forming electrically conductive vias in at least some of the chips such that some of the chips can be electrically connected to others of the chips, arranging the chips such that: some are coplanar in a first plane, at least one other lies in a second plane parallel to those in the first plane, and at least one of the chips in the first plane is connected to at least one of the chips in the second plane; and electrically interconnecting corresponding chips of the multiple discrete chips using the vias.

Claims

1. A device, comprising:

a first chip positioned on a first level; and

a second chip and a third chip positioned on a second level;

wherein the second chip has a first through-chip via and is coupled to the first chip through the first through-chip via;

wherein at least a portion of the second chip and at least a portion of the third chip overlap the first chip; and

wherein the first through-chip via includes;

a first annulus of insulating material;

a first annulus of a first electrically-conductive material bounding an outer surface of the first annulus of insulating material;

a second annulus of a second electrically-conductive material bounding an inner surface of the first annulus of insulating material;

a second annulus of insulating material within the second annulus of a second electrically-conductive material; and

a third electrically-conductive material within the second annulus of insulating material.

2. The device of claim 1, wherein the third chip has a second through-chip via and is coupled to the first chip through the second through-chip via.

3. The device of claim 2, wherein the second chip and the third chip are coplanar.

4. The device of claim 2, further comprising a fourth chip positioned on the first level, wherein the fourth chip is coupled to the second chip through the first through-chip via, and wherein the fourth chip is coupled to the third chip through the second through-chip via.

5. The device of claim 2, further comprising a fourth chip positioned on a third level, wherein the fourth chip is coupled to the second chip through the first through-chip via, and wherein the fourth chip is coupled to the third chip through the second through-chip via.

6. The device of claim 5, further comprising a fifth chip having a third through-chip via, wherein the fifth chip is positioned on the second level, and wherein the fifth chip is coupled to both the second chip and the fourth chip through the third through-chip via.

7. The device of claim 2, wherein the first chip comprises a microprocessor, wherein the second chip comprises a memory, and wherein the third chip comprises an input/output device.

8. The device of claim 2, wherein at least two of the first, second, and third chips have different operating speeds.

9. The device of claim 8, wherein the first chip comprises a microprocessor, wherein the second chip comprises a first cache memory, and wherein the third chip comprises a second cache memory.

10. The device of claim 1, wherein the first chip comprises a first processing device, wherein the second chip comprises a second processing device, and wherein the third chip comprises a third processing device.

11. The device of claim 2, wherein at least two of the first, second, and third chips have different semiconductor technologies.

12. The device of claim 2, wherein at least two of the first, second, and third chips have different operating voltages.

13. The device of claim 1, wherein the first, second, and third electrically-conductive materials are electrically isolated from each other.

14. A system, comprising:

a first chip positioned on a first level; and

a second chip and a third chip each positioned on a level different from the first level;

wherein the first chip overlaps only a portion of each of the second and third chips;

wherein the first chip is electrically coupled to at least one of the second or third chips through a through-chip via in one of the first, second, or third chip; and

wherein the through-chip via includes;

a first annulus of insulating material;

a first annulus of a first electrically-conductive material bounding an outer surface of the first annulus of insulating material;

a second annulus of a second electrically-conductive material bounding an inner surface of the first annulus of insulating material;

a second annulus of insulating material within the second annulus of a second electrically-conductive material; and

a third electrically-conductive material within the second annulus of insulating material.

15. The system of claim 14, wherein the second and third chips are positioned on substantially the same level.

16. The system of claim 15, wherein the second and third chips have different thicknesses.

17. The system of claim 15, wherein the second and third chips are substantially coplanar.

18. The system of claim 14, wherein the first annulus of electrically-conductive material is configured to be electrically grounded, the second annulus of electrically-conductive material is configured to carry a first signal, and the third electrically-conductive material is configured to carry a second signal different from the first signal.

19. The system of claim 14, wherein the first chip spans over a gap between the second and third chips.

20. The system of claim 14, wherein the first chip is further electrically coupled to at least one of the second or third chips through a rigid contact that penetrates into a malleable contact.

21. The system of claim 20, wherein the malleable contact is configured to deform under a pressure at a temperature below a melting point of the malleable contact.