Stacked-die electronics package with planar and three-dimensional inductor elements

• US 7,932,590 B2
• Filed: 07/13/2006
• Issued: 04/26/2011
• Est. Priority Date: 07/13/2006
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Lam, Ken M.
• Primary Examiner(s): Fahmy; Wael M
• Assistant Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US11/457,409
• Publication Number:
  US 20080054428A1
• Time in Patent Office: 1,748 Days
• Field of Search: 257/686, 257/678, 257/687, 257/700, 257/777, 257/707, 257/684, 257/690, 257/E23.001, 257/E23.194
• US Class Current: 257/686
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Claims

1. An integrated circuit device comprising:

a package substrate;

a first substrate having a front side and a back side, the front side of the first substrate having one or more integrated circuit devices and a plurality of bond pads fabricated thereon, the first substrate being mounted to the package substrate;

a second substrate having a front side, a back side, and a smaller area than the first substrate, the front side of the second substrate having one or more integrated circuit devices fabricated thereon, the second substrate being mounted to the first substrate;

at least one passive component fabricated onto the back side of the second substrate, the at least one passive component being comprised of a metal structure;

a first electrical conductor configured to allow electrical communications between the at least one passive component of the second substrate and at least one of the one or more integrated circuit devices of the first substrate;

a second electrical conductor configured to allow electrical communications between the second substrate and the first substrate;

a third electrical conductor configured to allow electrical communications between the first substrate and the package substrate, wherein the second electrical conductor and the third electrical conductor comprise a plurality of wire bonds;

a first adhesive material to bond the back side of the first substrate to the package substrate;

a second adhesive material to bond the back side of the second substrate to the front side of the first substrate; and

an encapsulant formed over the package substrate, the first substrate, the second substrate and the plurality of wire bonds.

2. The integrated circuit device of claim 1, wherein the at least one passive component is an inductor.

3. The integrated circuit device of claim 1, wherein the metal structure is comprised substantially of copper.

4. The integrated circuit device of claim 1, further comprising:

a dielectric material formed over the back side of the second substrate; and

a metal seed layer formed between the dielectric material and the metal structure.

5. The integrated circuit device of claim 4, wherein the dielectric material is a high-k dielectric.

6. The integrated circuit device of claim 4, wherein the metal seed layer is comprised substantially of titanium-tungsten.

7. An integrated circuit device comprising:

a package substrate;

a first substrate having a front side and a back side, the front side of the first substrate having one or more integrated circuit devices and a plurality of bond pads fabricated thereon, the first substrate being mounted to the package substrate;

a second substrate having a front side, a back side, and a smaller area than the first substrate, the front side of the second substrate having one or more integrated circuit devices fabricated thereon, the second substrate being mounted to the first substrate;

a first portion of at least one passive component fabricated onto the back side of the second substrate, the first portion of the at least one passive component being comprised of a first metal structure;

a second portion of the at least one passive component fabricated onto the front side of the first substrate, the second portion of the at least one passive component being comprised of a second metal structure formed to mirror the first portion of the at least one passive component;

a first electrical conductor configured to allow electrical communications between the first and second portions of the at least one passive component;

a second electrical conductor configured to allow electrical communications between the second substrate and the first substrate;

a third electrical conductor configured to allow electrical communications between the first substrate and the package substrate, wherein the second electrical conductor and the third electrical conductor comprise a plurality of wire bonds;

a first adhesive material to bond the back side of the first substrate to the package substrate;

a second adhesive material to bond the back side of the second substrate to the front side of the first substrate; and

an encapsulant formed over the package substrate, the first substrate, the second substrate and the plurality of wire bonds.

8. The integrated circuit device of claim 7, wherein the at least one passive component is an inductor.

9. The integrated circuit device of claim 7, further comprising:

a dielectric material formed over the back side of the second substrate; and

a metal seed layer formed between the dielectric material and the first metal structure.

10. An integrated circuit device comprising:

a package substrate;

a first substrate having a front side and a back side, the front side of the first substrate having one or more integrated circuit devices and a plurality of bond pads fabricated thereon, the first substrate being mounted to the package substrate;

a second substrate having a front side, a back side, and a smaller area than the first substrate, the front side of the second substrate having one or more integrated circuit devices fabricated thereon, wherein the first and second substrates are in a stacked relationship with the front side of the first substrate positioned adjacent the back side of the second substrate, the second substrate being mounted to the first substrate;

at least one passive component fabricated onto the back side of the second substrate and being electrically coupled to one or more integrated circuit devices on the front side of the first substrate;

a first electrical conductor configured to allow electrical communications between the second substrate and the first substrate;

a second electrical conductor configured to allow electrical communications between the first substrate and the package substrate, wherein the first electrical conductor and the second electrical conductor comprise a plurality of wire bonds;

a first adhesive material to bond the back side of the first substrate to the package substrate;

a second adhesive material to bond the back side of the second substrate to the front side of the first substrate; and

an encapsulant formed over the package substrate, the first substrate, the second substrate and the plurality of wire bonds.

11. The integrated circuit device of claim 10, wherein the at least one passive component is an inductor.

12. The integrated circuit device of claim 10, further comprising:

a dielectric material formed over the back side of the second substrate; and

a metal seed layer formed between the dielectric material and the at least one passive component that comprises a metal structure.

13. The integrated circuit device of claim 12, wherein the metal structure is comprised substantially of copper.