Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board

• US 7,932,612 B2
• Filed: 08/18/2009
• Issued: 04/26/2011
• Est. Priority Date: 03/10/1997
• Status: Expired due to Fees

• Current Assignee: Advanced Interconnect Systems Limited (Vector Capital Corporation)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hashimoto, Nobuaki
• Primary Examiner(s): Thai; Luan C
• Application Number:
  US12/543,221
• Publication Number:
  US 20090302467A1
• Time in Patent Office: 616 Days
• Field of Search: 257/777, 257/685, 257/686, 257/E27.137, 257/E27.144, 257/E27.161
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device having a semiconductor chip with electrodes, a stress-relieving layer prepared on the semiconductor chip, a wire formed across the electrodes and the stress-relieving layer, and solder balls formed on the wire over the stress-relieving layer; and a bare chip as a second semiconductor device to be electrically connected to the first semiconductor device.

Claims

1. An integrated type semiconductor device comprising:

a first semiconductor device that includes a first semiconductor chip, a first electrode, a second electrode, a first resin layer, a first wire, a second wire, and an external electrode, the first electrode and the second electrode being formed on a first surface of the first semiconductor chip, the first wire being electrically connected to the first electrode, a first portion of the first wire being formed on the first surface of the first semiconductor chip, the first resin layer being formed on the first surface of the first semiconductor chip in a region avoiding at least a part of the first wire, the second wire being electrically connected to the second electrode, a first portion of the second wire being formed on the first resin layer, the external electrode being formed on the first portion of the second wire; and

a second semiconductor device that includes a second semiconductor chip, a third electrode, and a bump, the third electrode being formed on a first surface of the second semiconductor chip, the bump being electrically connected to the third electrode, the bump being formed on the first portion of the first wire, the first surface of the second semiconductor chip facing the first surface of the first semiconductor chip.

2. The integrated type semiconductor device according to claim 1, further comprising:

a third wire that connects the third electrode and the bump.

3. The integrated type semiconductor device according to claim 2, further comprising:

a second resin layer that is formed between the third wire and the first surface of the second semiconductor chip.

4. The integrated type semiconductor device according to claim 3, the bump overlapping the second resin layer.

5. The integrated type semiconductor device according to claim 1, further comprising:

a radiator that is attached to a second surface of the first semiconductor chip opposite to the first surface of the first semiconductor chip.

6. The integrated type semiconductor device according to claim 1, further comprising:

a third resin layer that is formed between the first semiconductor chip and the second semiconductor chip.

7. The integrated type semiconductor device according to claim 6, a third surface of the second semiconductor chip connecting the first surface of the second semiconductor chip and a second surface of the second semiconductor chip opposite to the first surface of the second semiconductor chip, the third resin layer covering at least a part of the third surface of the second semiconductor chip.

8. An integrated type electronic component comprising:

a first electronic component that includes a first element chip, a first electrode, a second electrode, a first resin layer, a first wire, a second wire, and an external electrode, the first electrode and the second electrode being formed on a first surface of the first element chip, the first wire being electrically connected to the first electrode, a first portion of the first wire being formed on the first surface of the first element chip, the first resin layer being formed on the first surface of the first element chip in a region avoiding at least a part of the first wire, the second wire being electrically connected to the second electrode, a first portion of the second wire being formed on the first resin layer, the external electrode being formed on the first portion of the second wire; and

a second electronic component that includes a second element chip, a third electrode, and a bump, the third electrode being formed on a first surface of the second element chip, the bump being electrically connected to the third electrode, the bump being formed on the first portion of the first wire, the first surface of the second element chip facing the first surface of the first element chip.