Charge pump circuit

• US 7,932,770 B2
• Filed: 02/07/2008
• Issued: 04/26/2011
• Est. Priority Date: 02/07/2007
• Status: Active Grant

• Current Assignee: Cetus Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Yamahira, Seiji, Tomita, Yasuhiro
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US12/027,593
• Publication Number:
  US 20080186081A1
• Time in Patent Office: 1,174 Days
• Field of Search: None
• US Class Current: 327/536
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/077 with parallel connected charge pump stages

Abstract

Each of a plurality of pump stages has an input node and an output node and performs a charge pump operation in response to any one of the first and second clock signals. The plurality of pump stages include a first pump stage, in which a charge transfer transistor is connected between the input node and the output node. One end of a pump capacitor is connected to the output node, and the other end is supplied with one of the first and second clock signals corresponding to the first pump stage. A connection switcher connects to the gate of the charge transfer transistor any one of the output node of a pump stage which is supplied with one of the clock signals corresponding to the first pump stage and the input node of a pump stage which is supplied with the other clock signal not corresponding to the first pump stage and which is included in a pump stage row not including the first pump stage.

Claims

1. A charge pump circuit which performs a charge pump operation in response to complementary first and second clock signals to generate a pumped voltage, the charge pump circuit comprising:

a first pump stage arranged in a first pump stage row and in a first pump cell; and

a second pump stage arranged in a second pump stage row different from the first pump stage row and in the first pump cell, wherein;

each of the first pump stage and the second pump stage includes;

an input node;

an output node;

a charge transfer transistor, one end of which is connected to the output node, and the other end of which is connected to the input node;

a pump capacitor, one end of which is connected to the output node, and the other end of which receives one of the first and second clock signals; and

a connection switcher connected to a gate of the charge transfer transistor and having two control nodes,

the input node of the first pump stage and the output node of the second pump stage are connected to said two control nodes of the connection switcher of the first pump stage, respectively, and

the pump capacitor of the first pump stage receives one of the first and second clock signals and the pump capacitor of the second pump stage receives the other one of the first and second clock signals.

2. The charge pump circuit of claim 1, wherein

the connection switcher of the first pump stage switches a voltage between a voltage of the output node of the first pump stage and a voltage of the input node of the second pump stage to control the charge transfer transistor of the first pump stage.

3. A charge pump circuit which performs a charge pump operation in response to complementary first and second clock signals to generate a pumped voltage, the charge pump circuit comprising:

a first pump stage arranged in a first pump stage row and in a first pump cell; and

a second pump stage arranged in a second pump stage row different from the first pump stage row and in the first pump cell, wherein;

each of the first pump stage and the second pump stage includes;

an input node;

an output node;

a charge transfer transistor, one end of which is connected to the output node, and the other end of which is connected to the input node;

a pump capacitor, one end of which is connected to the output node, and the other end of which receives one of the first and second clock signals; and

a connection switcher connected to a gate of the charge transfer transistor and having two control nodes,

the output node of the first pump stage and the input node of the second pump stage are connected to said two control nodes of the connection switcher of the first pump stage, respectively, and

the pump capacitor of the first pump stage receives one of the first and second clock signals and the pump capacitor of the second pump stage receives the other one of the first and second clock signals.

4. The charge pump circuit of claim 3, wherein

the connection switcher of the first pump stage switches a voltage between a voltage of the input node of the first pump stage and a voltage of the output node of the second pump stage to control the charge transfer transistor of the first pump stage.

5. A charge pump circuit which performs a charge pump operation in response to complementary first and second clock signals to generate a pumped voltage, the charge pump circuit comprising:

a first pump stage arranged in a first pump stage row and in a first pump cell; and

a second pump stage arranged in a second pump stage row different from the first pump stage row and in the first pump cell; and

an analog comparator circuit, wherein;

each of the first pump stage and the second pump stage includes;

an input node;

an output node;

a first charge transfer transistor, one end of which is connected to the output node, and the other end of which is connected to the input node;

a pump capacitor, one end of which is connected to the output node, and the other end of which receives one of the first and second clock signals; and

a connection switcher connected to a gate of the first charge transfer transistor, and

the analog comparator circuit compares a voltage of the input node of the first pump stage with a voltage of the input node of the second pump stage, and

an output node of the analog comparator circuit is connected to a control node of the connection switcher of the first pump stage and to a control node of the connection switcher of the second pump stage, and

the pump capacitor of the first pump stage receives one of the first and second clock signals and the pump capacitor of the second pump stage receives the other one of the first and second clock signals.

6. The charge pump circuit of claim 5, further comprising:

a second charge transfer transistor, one end of which is connected to the input node of the first pump stage, and the other end of which is connected to the first charge transfer transistor of the first pump stage; and

a third charge transfer transistor, one end of which is connected to the input node of the second pump stage, and the other end of which is connected to the first charge transfer transistor of the second pump stage.

7. The charge pump circuit of claim 5, wherein

the connection switcher of the first pump stage switches a voltage between a voltage of the output node of the first pump stage and a voltage of the input node of the second pump stage to control the first charge transfer transistor of the first pump stage.

8. A charge pump circuit which performs a charge pump operation in response to complementary first and second clock signals to generate a pumped voltage, the charge pump circuit comprising:

a first pump stage arranged in a first pump stage row and in a first pump cell; and

a second pump stage arranged in a second pump stage row different from the first pump stage row and in the first pump cell; and

an analog comparator circuit, wherein;

each of the first pump stage and the second pump stage includes;

an input node;

an output node;

a first charge transfer transistor, one end of which is connected to the output node, and the other end of which is connected to the input node;

a pump capacitor, one end of which is connected to the output node, and the other end of which receives one of the first and second clock signals; and

a connection switcher connected to a gate of the first charge transfer transistor, and

the analog comparator circuit compares a voltage of the output node of the first pump stage with a voltage of the output node of the second pump stage, and

an output node of the analog comparator circuit is connected to a control node of the connection switcher of the first pump stage and to a control node of the connection switcher of the second pump stage, and

the pump capacitor of the first pump stage receives one of the first and second clock signals and the pump capacitor of the second pump stage receives the other one of the first and second clock signals.

9. The charge pump circuit of claim 8, further comprising:

a second charge transfer transistor, one end of which is connected to the input node of the first pump stage, and the other end of which is connected to the first charge transfer transistor of the first pump stage; and

a third charge transfer transistor, one end of which is connected to the input node of the second pump stage, and the other end of which is connected to the first charge transfer transistor of the second pump stage.

10. The charge pump circuit of claim 8, wherein

the connection switcher of the first pump stage switches a voltage between a voltage of the input node of the first pump stage and a voltage of the output node of the second pump stage to control the first charge transfer transistor of the first pump stage.