Frequency and phase locked loop synthesizer

• US 7,932,784 B1
• Filed: 09/13/2007
• Issued: 04/26/2011
• Est. Priority Date: 03/17/2005
• Status: Expired due to Fees

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Farlow, William J., Humphreys, Scott Robert, Janesch, Stephen T.
• Primary Examiner(s): Chang; Joseph
• Application Number:
  US11/854,917
• Time in Patent Office: 1,321 Days
• Field of Search: 331/10, 331/11
• US Class Current: 331/10
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

The present invention is a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. The FPLL synthesizer includes a variable frequency oscillator, which is controlled by FLL circuitry during the FLL operating mode or by PLL circuitry during the PLL operating mode. The FLL circuitry includes frequency division circuitry for reducing the frequency of the output signal, frequency detection circuitry for measuring the frequency error of the frequency reduced output signal, and a loop filter to control the bandwidth of an FLL control loop formed by the FLL circuitry and the variable frequency oscillator.

Claims

1. A radio frequency (RF) circuit comprising:

a first frequency-locked loop (FLL), which during a first FLL operating mode is adapted to;

receive a first reference signal having a first reference frequency;

provide a first frequency-reduced output signal having a first reduced output frequency, which is approximately equal to a first output frequency divided by a first constant; and

provide a first output signal having the first output frequency, which is based on a difference between the first reduced output frequency and the first reference frequency;

a first phase-locked loop (PLL), which during a first PLL operating mode is adapted to;

receive a second reference signal; and

provide the first output signal, which is based on a phase difference between the first output signal and the second reference signal, wherein the first FLL provides coarse tuning of a frequency of the first output signal during the first FLL operating mode and the first PLL provides fine tuning of a frequency of the first output signal during the first PLL operating mode;

a first variable frequency oscillator adapted to;

receive a first control signal and a second control signal; and

provide the first output signal having the first output frequency, which is based on at least one of the first control signal and the second control signal;

a first frequency reduction circuit, which during the first FLL operating mode is adapted to;

receive the first output signal; and

provide the first frequency-reduced output signal;

a first frequency detector circuit, which during the first FLL operating mode is adapted to;

receive the first frequency-reduced output signal and the first reference signal; and

provide a first frequency error signal, which is based on the difference between the first reduced output frequency and the first reference frequency;

a first loop filter circuit, which during the first FLL operating mode is adapted to;

receive and filter the first frequency error signal to create a first filtered frequency error signal; and

provide the first control signal based on the first filtered frequency error signal; and

PLL circuitry, which during the first PLL operating mode is adapted to;

receive one of the first output signal and the first frequency-reduced output signal, and a second reference signal having a second reference frequency; and

provide the second control signal based on the one of the first output signal and the first frequency-reduced output signal, and further based on the second reference signal.

2. The RF circuit of claim 1 wherein the second reference signal is approximately identical to the first reference signal.

3. The RF circuit of claim 1 wherein:

during the PLL operating mode;

the first frequency reduction circuit is further adapted to;

receive the first output signal; and

provide the first frequency-reduced output signal having the first reduced output frequency, which is approximately equal to the first output frequency divided by the first constant; and

the PLL circuitry is further adapted to;

receive the first frequency-reduced output signal; and

provide the second control signal further based on the first frequency-reduced output signal.

4. The RF circuit of claim 1 wherein the first frequency reduction circuit comprises a first divider circuit adapted to receive the first output signal and provide the first frequency-reduced output signal based on frequency division of the first output signal.

5. The RF circuit of claim 1 wherein the first frequency reduction circuit comprises:

an RF mixer adapted to receive the first output signal and a local oscillator (LO) signal having an LO frequency, and provide an RF mixer output signal based on mixing the first output signal and the LO signal; and

a mixer filter circuit adapted to receive the RF mixer output signal and provide the first frequency-reduced output signal based on filtering the RF mixer output signal.

6. The RF circuit of claim 5 wherein an initial value of the first output frequency is less than approximately a sum of the LO frequency and a desired intermediate frequency.

7. The RF circuit of claim 5 wherein an initial value of the first output frequency is greater than a threshold value, which is approximately equal to a sum of the LO frequency minus a desired intermediate frequency.

8. The RF circuit of claim 5 further comprising an LO synthesizer adapted to provide a second output signal having a second output frequency, wherein the LO signal and the first reference signal are based on the second output signal.

9. The RF circuit of claim 8 wherein coarse tuning the first variable frequency oscillator begins approximately upon or after completion of coarse tuning the LO synthesizer.

10. The RF circuit of claim 8 wherein coarse tuning of the first variable frequency oscillator begins based on timing from tuning the LO synthesizer.

11. The RF circuit of claim 8 wherein coarse tuning the first variable frequency oscillator begins approximately before completion of fine tuning the LO synthesizer.

12. The RF circuit of claim 8 wherein an initial tuning value for the first variable frequency oscillator is based on a completion tuning value of the LO synthesizer.

13. A radio frequency (RF) circuit comprising:

a first frequency-locked loop (FLL) comprising discrete tuning elements, and during a first FLL operating mode is adapted to;

receive a first reference signal having a first reference frequency;

select at least one of the discrete tuning elements based on a first output frequency and the first reference frequency; and

provide a first output signal having the first output frequency, which is based on the select at least one of the discrete tuning elements;

a first phase-locked loop (PLL), which during a first PLL operating mode is adapted to;

receive a second reference signal; and

provide the first output signal, which is based on a phase difference between the first output signal and the second reference signal, wherein the first FLL provides coarse tuning of a frequency the first FLL operating mode and the first PLL provides fine tuning of a frequency of the first output signal during the first PLL operating mode;

a first variable frequency oscillator;

comprising the discrete tuning elements; and

adapted to;

receive a first control signal and a second control signal; and

provide the first output signal having the first output frequency, which is based on at least one of the first control signal and the second control signal,

wherein the select at least one of the discrete tuning elements is based on the first control signal;

a first frequency detector circuit, which during the first FLL operating mode is adapted to;

receive one of a derived signal based on the first output signal having a derived output frequency and the first output signal;

receive the first reference signal; and

provide a first frequency error signal, which is based on a difference between one of the derived output frequency and the first output frequency, and the first reference frequency;

a first loop filter circuit, which during the first FLL operating mode is adapted to;

receive and filter the first frequency error signal to create a first filtered frequency error signal; and

provide the first control signal based on the first filtered frequency error signal; and

PLL circuitry, which during the first PLL operating mode is adapted to;

receive one of the first output signal and the derived output signal, and the second reference signal having a second reference frequency; and

provide the second control signal based on the one of the first output signal and the derived output signal, and further based on the second reference signal.

14. The RF circuit of claim 13 wherein the second reference signal is approximately identical to the first reference signal.

15. The RF circuit of claim 13 wherein the first frequency detector circuit comprises:

a digital sequence generating circuit adapted to provide a sequence count based on the one of the first output signal and the derived output signal;

a digital sequence decoder adapted to receive and decode the sequence count to provide a binary decoded count signal; and

a first difference circuit adapted to receive a first value of the binary decoded count signal and a second value of the binary decoded count signal,

wherein the first frequency error signal is further based on a second difference between the first value and the second value.

16. The RF circuit of claim 15 wherein the digital sequence generating circuit is adapted to receive a clock signal, such that the sequence count changes by a single-bit for each clock from the clock signal.

17. The RF circuit of claim 16 wherein the digital sequence generating circuit comprises a Gray code counter and the digital sequence decoder comprises a Gray code decoder.

18. The RF circuit of claim 13 wherein the first loop filter circuit comprises a gain circuit adapted to receive a first loop filter signal based on the first frequency error signal, and provide an amplified first loop filter signal, wherein a gain factor times a magnitude of the first loop filter signal is approximately equal to a magnitude of the amplified first loop filter signal, and the first filtered frequency error signal is based on the amplified first loop filter signal.

19. The RF circuit of claim 18 wherein the first FLL operating mode further comprises a first acquisition mode and a first average and interpolate mode, and a magnitude of the gain factor during the first acquisition mode is greater than a magnitude of the gain factor during the first average and interpolate mode.

20. The RF circuit of claim 19 wherein the first control signal is a digital signal having one of a plurality of digital values, which changes by a first amount during the first acquisition mode and by a second amount during the first average and interpolate mode.

21. The RF circuit of claim 13 wherein the first loop filter circuit comprises an adder adapted to receive a first loop filter signal based on the first frequency error signal and a bias signal, and adapted to provide a second loop filter signal based on the first loop filter signal and the bias signal, wherein the first filtered frequency error signal is based on the second loop filter signal;

and when the first frequency error signal is approximately zero, a change in a magnitude of the second loop filter signal is based on the bias signal.